Enables the fractional-N (FRACN) setting for PLL1 in the STM32H5XX
clock driver.
This feature allows achieving a system clock frequency of 250 MHz from
an 8 MHz `clk_hse`.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add support for STM32H757 SoC, which shares its design
with STM32H747 with added cryptography peripherals.
Signed-off-by: Grzegorz Runc <g.runc@grinn-global.com>
Unlike the RP2040, the RP2350 has multiple tick generators that need to
be started. Start TIMER0 and TIMER1 tick generators during
clock_control_init.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Add support for SoC-specific clock ids and update the initialization
function to support the existing RP2040 and add support for the RP2350.
clock_control_rpi_pico.c uses numerical values for clock ids taken from
rpi_pico_clock.h which are the "clock generator". For the RP2350 these
values are different for some of the same logical clock sources, as well
as the RP2040 and RP2350 having different clock sources available.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
This is a follow-up to commit fe0e2dbc60.
If `nrf_clock_control_request_sync()` ends up with a timeout, before
returning it must cancel the request that was not fulfilled on time.
Otherwise, the request may actually finish successfully a bit later,
but the caller will not be aware that the clock needs to be released
(since the call resulted in an error). And actually even more serious
problem is that because the `req` structure is placed on stack, after
the function returns, the contents of this structure will be probably
overwritten with some other data, so if the request finishes at that
point, an attempt to execute the callback function pointed by this
structure will most likely cause a crash.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The clock_stm32_ll_common.c function set_up_plls calls
LL_RCC_PLL_Disable();and it was not waiting for the
disable to complete before trying to configure
the pll sysclock which creates a race condition for
pll configuration.The wait for re-enabling the RCC pll
is already there, it was just missing the wait for
the disable before configuration. Also added the wait for PLL2.
Signed-off-by: Benjamin Curtis Byers <ben.byers@ubcobikes.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
There were redundant code in full_irq_lock(), full_irq_unlock()
functions that supposed to be used when ZLI IRQs are disabled.
These functions are compiled in only when CONFIG_ZERO_LATENCY_IRQS
is set, hence the non-ZLI execution path was never included
in final binaries.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
The nrf-hsfll was previously the only supported HSFLL clock, hence it
was not namespaced fully. Since we added nrf-hsfll-global, we should
add the namespace to nrf-hsfll as well.
Updates drivers and devicetree uses of HSFLL as well.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The clock controller/manager registers are updated with
the correct divider values by bootloader via hand-off
data, so now we can use the clock controller to get the
clock value of each peripheral during the run time.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Add a function to compute the clock48 from the clock tree
of a stm32f412/f413 mcu. The value depends on its clock source
Requires to identify the PLL source HSE or HSI.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the configuration of the PLL Q divider of main PLL
and I2S_Q of the PLLI2S toset the PLL48MHz clock which feeds
the USB, SDMMC, RNG through the RCC_DCKCFGR2 register.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Implement the zero latency interrupt safe APIs to the HFXO clock
commonly used by the bluetooth stach from zero latency interrupt
context.
Co-authored-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
It may be required to get information if NRF LF clock control calibration
is in progress. Some time sensitive operations could benefit from this
information.
The commit adds simple function that provides the information.
The function is nRF platform specific.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Update init function so APPCPU could not altere the clock setup.
Fix build in case if no inter-cpu module is selected.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Support specifying divided clock buses by introduction of
STM32_CLOCK_DIV(div) macro. This macro can be used in devicetree to define
clock source of peripherals.
HSE is selected in devicetree using:
<&rcc STM32_SRC_HSE ...>;
HSE/2 can now be selected with:
<&rcc (STM32_SRC_HSE | STM32_CLOCK_DIV(2)) ...>;
This allows to use clock_control_get_rate() API in peripherals in order to
get desired clock rate.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Due to clock designed on RT1180 has some different with other platforms,
so add macro and handle the clock difference in mcux_ccm_get_subsys_rate.
TPM1 use Bus_Aon as clock root.
TPM3 use Bus_Wakeup as clock root.
Other instances have independent clock root.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Rely on the DTS to get the MCO input source clock and prescaler.
DTS configuration has been introduced and Kconfig method
deprecated two releases before and can be then safely removed.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The stm32F41x have a PLLI2S M divider for their PLL I2S
but others like the stm32F401 or stm32F74x have the PLL M
divider from the main PLL : might affect the sysclock.
LL Function is the same for configuring the PLL I2S but
parameter could depends on the stm32 serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
No in-tree board uses this driver's pinctrl functionality, and every
RP2040-based board was configuring this to be an empty node in the
device tree, so remove them.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
RESETS_RESET_PLL_USB_BITS was logically or'd twice and 'unreset'ting
PWM doesn't seem to be required, based on the contents of the SDK.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Due to the possibility of simultaneous accesess to LRCCONF registers,
additional management is required.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
This commit adds the clock driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
The `Kconfig.defconfig` is not good place for put `select PINCTRL`.
Drop `select PINCTL` from `Kconfig.defconfig` and add it at each
driver's Kconfig.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The NXP PORT pinmuxing peripheral is reused across the MCX, S32, and
Kinetis lines. Rename the compatible from the family-specific
nxp,kinetis-pinctrl to a more generic nxp,port-pinctrl to reflect the
actual name for the IP block used within reference manuals.
Update the NXP HAL revision to include a change to use the new Kconfig
name for the PORT pinctrl driver
Update the MAINTAINERS.yml path, as there are no longer any NXP drivers
matching the string "drivers/*/*kinetis*
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove the renesas,ra-clock-generation-circuit driver, which is no longer
needed after migrating to the FSP-based implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Disable every PLL before configuration. That allows
an application to reconfigure PLLs after a bootloader
configuration.
Don't disable the PLL clock if it is used by (Q|O)SPI
when executing from external memory. That will lead
to a stall.
Note: when (Q|O)SPI runs from PLL, the bootloader
dictates the clock configuration. There is no clock
reconfiguration support for memory map mode in
(Q|O)SPI drivers.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Add npcm clock control driver.
Signed-off-by: James Chiang <cpchiang1@nuvoton.com>
Signed-off-by: Joseph Liu <kwliu@nuvoton.com>
Signed-off-by: Alan Yang <tyang1@nuvoton.com>
The new update of clock device tree make the pll p q r clock
source cannot be choose by other node
This fix add 1 new dts binding for pll out p q r out line
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
