Add support to wake up from sleep mode by START condition when i2c
is configured to target mode.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
For code clarity, this commit adjusts the use of `return` statements
in functions with a void return type as follows:
- Transform `return foo();` into separate statements:
`foo();`
`return;`
- Remove unnecessary `return` statements when
they don't affect control flow.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
When the I2C is in the target mode and encounters the bus error, the
driver has to reset the bus to recover the I2C hardware. However, when
the hardware is disabled, the interrupt enable bits are also cleared
automatically by design. As a result, we need to enable the interrupts
after resetting the I2C hardware.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Employ a code spell checking tool to scan and correct spelling errors
in all files within the drivers/i2c directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add I2C target mode support for NPCX i2c driver. Verified with
i2c_target_api test suite on npcx9m6_evb.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The i2c_npcx_controller does not actually implement the i2c API, that's
implemented in the port driver and the controller one is in support of
that. This means there's no need to use the I2C specific instance
define, as that would end up adding the stats structure that would never
get used.
This was originally added in 7b1349cfe6.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
For NPCX SMB/I2C SMB modules in FIFO mode, the registers include:
* Common registers, offset 0x00-0x0f, accessible regardless of the value
of BNK_SEL
* Bank 0 registers, offset 0x10-0x1e, accessible if BNK_SEL is set to 0
* Bank 1 registers, offset 0x10-0x1e, accessible if BNK_SEL
is set to 1
In the current driver, it uses two structures, `smb_reg` and
`smb_fifo_reg`, to access `Common + Bank 0` and `Common + Bank 1`
registers. But It might be easy to misunderstand that they are two
different modules.
This CL tries to simplify this by the following steps:
1. Use `union` to combine `Bank 0/1` registers in the same structure.
2. Remove `smb_fifo_reg`. We needn't use two structures to present
SMB registers.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
When there is a timeout for an i2c transaction, the i2c driver should do
the recovery logic to make the bus and driver state machine go back to
idle. Otherwise, it will cause the following transaction to fail because
the state machine keeps in an inappropriate state.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add I2C bus recovery support by emitting 9 SCL clock pulses.
It implements the equivalent logic of the i2c_unwedge function in the
ChromiumOS legacy-EC.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
When an I2C transaction completes, the driver should clear all the FIFO
status. Otherwise, it has the chance to break the operation of the next
transaction. This commit sets the CLR_FIFO bit in the SMBFIF_CTS
register to clear all the FIFO status at the beginning of an I2C
transaction.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Deep Sleep mode stops SMB module clocks which could interrupt ongoing
I2C transactions, so have the I2C driver acquire a PM lock at the
beginning of a transaction and release it at the end in order to ensure
the module remains active.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Refactors the remaining I2C drivers to use the shared driver class
initialization priority configuration, CONFIG_I2C_INIT_PRIORITY, to
allow configuring I2C drivers separately from other devices. This is
similar to other driver classes.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
In the I2C ISR, it prints the error message when SMBST is set to an
unexpected value. However, we found a spurious interrupt which caused
the SoC to enter the ISR with SMBST=0. Because the spurious interrupt
will not break the I2C operation, this commit limits the error log to
print if SMBST is not equivalent to 0 to prevent a false alert.
Signed-off-by: Andrew McRae <amcrae@google.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This corrects the following:
1. The priority of type cast is lower than member access. So don't need
the redundant parentheses.
2. The macro should be added to the parentheses.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
The original parameter (k1) setting may let the I2C frequency be a
little bit higher than 100k Hz, which causes the timing Tsu:sta (set-up
time for a repeated START) to violate the spec. This change fixes the k1
parameter and also changes the HLDT to the suggested value in the
datasheet.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Adds the ability for I2C drivers to report synchronous transfer stats
using a I2C specific macro to define the device instance.
The macro creates a container for device_state which allows for per
instance device class common data structure to be used in the device
class api (ex: i2c.h). This is used to maintain per driver instance
stats for all i2c drivers. This is a reusable idea across other device
classes as desired.
Using Kconfig device class stats may be turned on/off individually
this way as well, in this case I2C_STATS.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add get_config function to NPCX I2C driver. The master mode is hardcoded
and get the speed from a controller.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Convert the various device_get_binding() calls used to get the device
clock node to use DEVICE_DT_GET. The latter is processed at link time,
so it should be a bit more efficient.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Currently there is no way to distinguish between a caller
explicitly asking for a semaphore with a limit that
happens to be `UINT_MAX` and a semaphore that just
has a limit "as large as possible".
Add `K_SEM_MAX_LIMIT`, currently defined to `UINT_MAX`, and akin
to `K_FOREVER` versus just passing some very large wait time.
In addition, the `k_sem_*` APIs were type-confused, where
the internal data structure was `uint32_t`, but the APIs took
and returned `unsigned int`. This changes the underlying data
structure to also use `unsigned int`, as changing the APIs
would be a (potentially) breaking change.
These changes are backwards-compatible, but it is strongly suggested
to take a quick scan for `k_sem_init` and `K_SEM_DEFINE` calls with
`UINT_MAX` (or `UINT32_MAX`) and replace them with `K_SEM_MAX_LIMIT`
where appropriate.
Signed-off-by: James Harris <james.harris@intel.com>
In the npcx i2c FIFO mechanism, the hardware will release SCL bus
immediately after the driver reads data from FIFO. That's why we need
to hold SCL bus before configuring the next transaction. Once it was
done, the driver release the bus for the next transaction.
But during the last transaction, the driver releases SCL first then
starts a STOP condition. At this moment, the SCL is pulled high by PU
resistance and driven to low for generating STOP condition later. This
additional clock might influence some i2c devices if they don't reset
their state machine after receiving STOP.
This CL fixes this issue by two steps:
1. Distinguish that it's the last read transaction with STOP condition?
2. If so, issue STOP condition before reading FIFO instead of holding
SCL bus. Then the hardware will generate it immediately after reading
FIFO.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL prevents the transaction result overwritten by the recovery
function. Even if the recovery mechanism succeeds, the upper layer still
needs to know why the transaction failed.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Since all fields' type in SMBST is R/W1C and RO, setting a single bit to
clear a specified event is a more suitable solution. Or we might clear
the other pending bits that occurred at the same moment unexpectedly.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL reset i2c event-completed semaphore before starting
transactions. Some interrupt events such as BUS_ERROR might change its
counter when i2c bus is idle. It causes that the driver cannot wait
for the event completed and return immediately.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Since the PU power rail of i2c bus might be gone at the initial state
after ec powered up, we might have no chance to get STOP condition. This
is because no i2c transactions occurred before its power rail is
restored. But it's crucial to reset the whole i2c module after i2c bus
is back to the idle state.
The original test suite for i2c recovery mechanism didn't consider this
case that initial i2c bus is low before ec powered on. Hence, this CL
fixed this symptom by:
1. Force i2c modules must proceed 'reset' step no matter we received
STOP condition or not.
2. Use Boolean for condition check to prevent misusage and meet MISRA.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The NPCX SMB modules provides full support for a two-wire SMBus/I2C
synchronous serial interface. Each SMBus/I2C interface is a two-wire
serial interface that is compatible with both Intel SMBus and Philips
I2C physical layer. There are 8 SMBus modules and 10 buses in NPCX7
series.
In NPCX7 series, the SMB5 and SMB6 modules contain a two-way switch to
support two separate SMBus/I2C buses (ports) with one SMB module
(controller) Please refer Section 4.7.2 in the datasheet. In order to
support it, this CL seperates the i2c driver into port and controller
drivers. The controller driver is in charge of i2c module operations
and internal state machine. The port driver is in charge of pin-mux
and connection between Zehpyr i2c api interface and controller driver.
All of modules have separate 32-byte transmit FIFO and 32-byte receive
FIFO buffers. These FIFO buffers reduce firmware overhead during long
SMBus transactions by allowing the Core to write or read more than one
data byte at a time to/from the SMB module.
The CL also includes:
— Add npcx i2c port/controller device tree declarations.
— Zephyr i2c api implementation.
— Add "i2c-0" aliases in npcx7m6fb.dts for i2c test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
