Increase the size of the main stack for BLE applications to avoid
stack overflow on STM32WB0x series. Beacon sample was considered as
a reference for the size increase.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
STM32WB0 series was missed when SoC initialization code was migrated
from SYS_INIT routines to the new soc_early_init_hook method
(c.f. commit c6a03606c2)
Update that series' initialization code to align it with all others.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Moves the LV_DRAW_DMA2D_HAL_INCLUDE to the soc instead of the development
kit since the hal include is the same across all boards using the soc.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
Add support for STM32H757 SoC, which shares its design
with STM32H747 with added cryptography peripherals.
Signed-off-by: Grzegorz Runc <g.runc@grinn-global.com>
This reverts commit b33b3b17f7, turns out
it's causing issues in CI all over the place, the condition needs more
thinking.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add a compiler warning when building for an STM32 series MCU with PM
enabled but STM32_ENABLE_DEBUG_SLEEP_STOP=y. That option greatly
increases the power consumption during sleep, which is probably
undesirable when building with PM=y, and it can be activated silently
as a side effect of other options (namely RTT) making it tricky to find
out.
Add a warning to expose the situation.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Wakeup pin indices are 1-based, but `LISTIFY` is 0-based. Consequently, the
last element of the pin-to-register-bit lookup table was never populated.
Signed-off-by: Samuel Coleman <samuel.coleman@rbr-global.com>
check if multiples UART instances with same irq are enabled
at same time then enable shared_interrupt handler.
set the default value of SHARED_IRQ_MAX_NUM_CLIENTS config if
we have more than 2 usarts instances enabled.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Release HSI CLK48 semaphore when going to sleep to allow C2 (M0)
core to start and stop clock as needed while C1 core is not running.
CLK48 is shared between RNG and USB. RNG is needed by M0 during BLE
advertisement. If semaphore is locked, C2 core can start it when it
needs to but not stop it.
Fixes zephyrproject-rtos#69955.
Signed-off-by: Jonny Gellhaar <jonny.gellhaar@prevas.se>
Put the default value for BT_AUTO_PHY_UPDATE and BT_AUTO_DATA_LEN_UPDATE
to "n" at SOC level since they cause "controller busy" due to starting
several parallel BLE procedures during connection by
"perform_auto_initiated_procedures" function. At the moment, ST controller
does not support parallelism, i.e. host should not initiate a new procedure
before previous one is completed.
Disable CONFIG_BT_HCI_ACL_FLOW_CONTROL at SOC level.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Files renaming done to better isolate zephyr related
functions from stm32 hal related functions
Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
Make the SMPS_MODE define visible from drivers by moving it to soc.h
This define is for example used by the ADC driver to determine if sampling
should be synchronized with the SMPS clock.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Enables the XSPIM2 rail when using GPIO bank N
Enables the XSPIM1 rail when using GPIO bank O or P
Enables the USBvoltage detector when using the GPIO M
Signed-off-by: Francois Ramu <francois.ramu@st.com>
DBGMCU clock handling was not optimal.
If it exists, enable it before dealing with debug configuration in one
block, then deactivate it after in another block.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Similarly to debug in stop mode, enable debug in sleep mode on H7 series,
as initially described by `STM32_ENABLE_DEBUG_SLEEP_STOP` option.
Not extending it further to other series as I won't be able to test.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
# Conflicts:
# soc/st/stm32/common/soc_config.c
HAL_Enable/DisableDBGStopMode() was one of the last usage of HAL
definitions from Legacy HAL APIs.
Use LL instead to harmonize code across series and remove this dependency.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The STM32WB06 and STM32WB07 SoCs do not support SMPS output current limit.
This makes the LL_PWR_SetSMPSPrechargeLimitCurrent function and all the
LL_PWR_SMPS_PRECH_LIMIT_CUR_xxx defines not visible when one of these SoCs
is selected, resulting in a build failure.
Fix this by only handling SMPS current limit when the feature is available.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
check if two or three I2C instances with same irq are enabled
at same time then enable shared_interrupt handler.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Rather setting the driver default in soc, make it directly at symbol
level rather than soc and clean up redundant `select` occurrences.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
CLOCK_CONTROL subsystem is expected to be enabled systematically on all
STM32 devices.
Make it a series default.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add support for the stm32h755 which is a close relative of
the stm32h745 with additional cryptography and hashing
peripherals.
Signed-off-by: Mike Banducci <michael.banducci@sandc.com>
For stm32 platforms where the sysclock is less or equal to
32MHz, the Ticks per second is reduced to 8000 (instead of
10000).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The total number of IRQs for this chip is 110.
Refer to the reference manual table 46 for IRQs.
Signed-off-by: Rahul Arasikere <arasikere.rahul@gmail.com>
This commit fixes a bug with the declaration of the Kconfig option
MEMC_STM32.
The option is defined in two files:
- `drivers/memc/Kconfig.stm32`, wich depends on
- `MEMC`
- `DT_HAS_ST_STM32_FMC_ENABLED`
-`soc/st/stm32/Kconfig.defconfig`, wich depends on
- `MEMC`
- `SOC_FAMILY_STM32`
So, if you have `CONFIG_MEMC=y` in your Kconfig options and you are on a
STM32 SoC, `CONFIG_MEMC_STM32` will be enabled, even if there is no
STM32 FMC enabled.
This Kconfig option causes the driver for the STM32 FMC to be compiled,
regardless of the presence of an enabled node for the FMC.
However, the driver fails to compile if there is no FMC node in the
devicetree. So, if you compile a project with `CONFIG_MEMC=y` on a board
with an STM32 SoC and no enabled FMC, the build will fail.
This commit deletes the Kconfig declaration in the `Kconfig.defconfig`,
as it isn't useful and is the one provoking the bug.
It also add in the `Kconfig.stm32` the compatible `st,stm32h7-fmc`, wich
use the same driver and so need to be enabled by the same Kconfig
option.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
SYSTEM_WORKQUEUE_STACK_SIZE increase is required to fix not
only BLE Ext Adv (70935), but also other BLE use cases according
STM32WBA HCI driver
Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
Some stm32 series, do not have a LL_DBGMCU_SetTracePinAssignment
function to enable trace IO port, this is the case with the
stm32h7 serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
LPTIM is not available in STOP3 mode, so RTC needs to be used instead.
This code usese similar approach as STM32WBAx for suspend to ram.
The STOP3 is disabled by default in device tree.
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
Convert the hci_stm32wba.c driver to the new HCI API. Unlike in most cases,
the devicetree node is already enabled on the SoC level (rather than board
level). This is in order to mirror how the Kconfig option was originally
enabled, i.e. on the SoC level.
Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
The drivers should be independent after the move to the new HCI driver
API. Having them as a choice also has unexpected consequences with some
drivers being unexpectedly enabled.
Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
