The samr21 is a samd21 with a builtin at86rf233 radio. Use the samd21 as
base for these SoC and drop all duplicated nodes.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The saml2x series provide USB to all SoC series. This moves the USB node
from saml21.dtsi to the base file saml2x.dtsi.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
When running tests on sam0 platform was detected that pinctrl for ADC
were not defined for some boards. To force an error at build time
nodes should be explicity disabled. This explicity disable nodes on
devicetree that require some user configuration.
In addition, the adc feature were excluded in some boards and
samr21-xpro was correct updated.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Keep a consistent order on the nodes definitions to make it easy to read
between all the SoC series.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add the ability to select littlefs disk version
to maintain backward compatibility
with existing littlefs
with the same major disk version.
Signed-off-by: Mikhail Siomin <victorovich.01@mail.ru>
LinkServer can flash only the first time, cannot flash again.
Fix it by setting default mcu security status as unsecure.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
The nrf-hsfll was previously the only supported HSFLL clock, hence it
was not namespaced fully. Since we added nrf-hsfll-global, we should
add the namespace to nrf-hsfll as well.
Updates drivers and devicetree uses of HSFLL as well.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add specific device model for global hsfll clock and update dts tree
to use specific model. The clock is not fixed, and configurable at
runtime to predefined frequencies specified by the platform.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Remove hard-coded clock values from device tree nodes,
instead read the clock values from the clock controller
during run time.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
The actual clock speed of the bus is partially determined by the
rising/falling edges of the SCL. These settings allow applications
to tune the clock based on board characteristics.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
Add a clk48Mhz node to the stm32f412 serie.
This clock is sourced by PLL_Q (default) or PLLI2S_Q
That 48MHz clock is used by the USB /SDMMC/RNG peripherals.
The sdmmc/SDIO clock is sourced by this CK48 (default)
or by the SYSCLOCK.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add power domains for EDMA0's channels 6, 7, 14, and 15.
For QM these are identified as IMX_SC_R_DMA_2_*, while
for QXP thy are identified as IMX_SC_R_DMA_0_*.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This has no address space and doesn't belong between peripheral
nodes. Move it up the DTSI for better visibility. No functional
change.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
imx8qm and imx8qxp have a couple of differences regarding
the peripheral address spaces and how the DT nodes are
configured, which is why using a generic DTSI (nxp_imx8.dtsi)
for the both of them is not right.
One of the differences between the two, which affects Zephyr
is the fact that irqstr's address space is different. Up until
now this has been dealt with at the board level (i.e:
imx8qxp_mek_mimx8qx6_adsp.dts), which is not right as this is not
board-specific, but rather soc-specific. Additionally, this
causes the following warning during compilation:
"unit address and first address in 'reg' (0x51080000) don't
match for /interrupt-controller@510a0000"
To fix this, add two new DTSIs: nxp_imx8qm and nxp_imx8qxp.
Each board (i.e: imx8qm_mek and imx8qxp_mek) will have to include
the DTSI for their soc instead of the generic DTSI (i.e: nxp_imx8).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
The Microchip CAP12xx series are available in 3, 6 or 8 channel versions.
Co-authored-by: Benjamin Cabé <kartben@gmail.com>
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
The reg address was not equal to the one in the node name, producing
a build warning.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Set AMP dts nodes (ipm, mbox, ...) to use fixed locations in reserved
memory areas. Those areas memories are delimited in the `memory.h`.
Size of the occupied areas can be calculated but the dts nodes addresses
needs to be set manually in every case.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This is the initial commit to support UART driver for Renesas RZ/G3S.
The driver only implements polling API for minimal support.
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/G3S
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This adds minimal support for a new SoC Renesas RZ/G3S
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
This commit adds the main DTS configurations required
to enable I3C support on STM32.
Signed-off-by: Mohammad Badawi <zephyr@exalt.ps>
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
LJ packages have 16 ADC channels vs 8 for SZ packages. Enhance
devicetree to account for this as well as conditional defines/code.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Due to Apollo3's internal bootloader, zephyr build is not able
to create correct flash address on linker.cmd while using
mcuboot. The PR configures flash-controller start address
to solve this problem.
Test board: rakwireless/rak11720
Test project: samples/subsys/mgmt/mcumgr/smp_svr
Signed-off-by: Sercan Erat <sercanerat@gmail.com>
This patch refactors the power management initialization for the SSP
driver across ACE15, ACE20, and ACE30 generations to align with the
recommended practices outlined in the documentation. The changes
include:
1. Replacing the conditional initialization of power management state
with a call to `pm_device_driver_init` in the `ssp_init` function.
2. Adding the `zephyr,pm-device-runtime-auto` property to the SSP nodes
in the device tree files for ACE15, ACE20, and ACE30.
3. Moving the power domain assignment for the SSP device in the device
tree. The previous configuration resulted in the device not being under
any power domain and being initialized as always ON.
These changes ensure that the SSP driver is initialized with the
appropriate power management state and that runtime power management is
automatically enabled based on the device tree configuration. The
functionality of the power management state remains unchanged, ensuring
consistent behavior.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
