zephyr/dts/riscv
Gerard Marull-Paretas e7b9c8c955 dts: gigadevice: gd32vf103: move interrupt-parent to soc node
There's no need to specify the interrupt parent on each node, it can be
defined at soc level node instead (same as in ARM parts with NVIC).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-08-25 09:09:51 +00:00
..
andes dts: riscv: andes: andes_v5_ae350: replaced smu with syscon 2022-08-23 10:15:50 +02:00
espressif esp32: dts: add RTC timer node 2022-07-27 09:48:33 +02:00
gigadevice dts: gigadevice: gd32vf103: move interrupt-parent to soc node 2022-08-25 09:09:51 +00:00
ite ITE: drivers/i2c: Add I2C FIFO mode 2022-08-23 10:16:36 +02:00
microsemi dts: riscv: microsemi-miv: define CLINT 2022-08-02 09:12:31 +02:00
openisa dts: riscv: Remove label property from devicetrees 2022-07-26 12:57:23 -05:00
sifive dts: riscv: sifive: use sifive,clint0 2022-08-02 09:12:31 +02:00
starfive dts: riscv: starfive: align clint description with Linux 2022-08-02 09:12:31 +02:00
telink dts: riscv: telink: add DT entry for machine timer 2022-08-02 09:12:31 +02:00
mpfs-icicle.dtsi include: add missing zephyr/ prefixes 2022-08-02 18:03:58 +01:00
neorv32.dtsi dts: riscv: neorv32: define machine timer 2022-08-02 09:12:31 +02:00
riscv32-litex-vexriscv.dtsi dts: riscv: Remove label property from devicetrees 2022-07-26 12:57:23 -05:00
virt.dtsi dts: riscv: virt: use sifive,clint0 2022-08-02 09:12:31 +02:00