m68ki_read_opcode_16 is both a different access path for instructions
(meaning we can decode addresses with certain assumptions), and also can be
implemented faster (always an aligned 16b read).
Currently used only on m68k_execute(), this macro allows a project
to flag functions that are performance-critica. For example, on
microcontroller builds certain functions might be decorated to
ensure the build locates them in faster types of memory.
For some projects, runtime selection of CPU type isn't required,
and burns both time and space. This config option allows a build-
time selection of CPU model.
The static decode jump table is built via m68kmake, and with a project
config can be used by the main runloop.
Add M68K_CYCLE_COUNTING to enable per-instruction cycle counts
versus accumulating a dummy (constant) cost per instruction.
Move the cycle-counting to a macro -- for now, CYCLE_COUNTING is only
supported when using DYNAMIC_INSTR_TABLES (as no static table gen
is provided yet).
Static jumptable saves 256K of RAM, and avoiding cycle counting
saves 320K!
An alternative to the runtime-generated decode jump table, this generates
one at build time. The dynamic one uses more RAM, and the static one
makes the binary bigger.
This is qualified on a new M68K_DYNAMIC_INSTR_TABLES option.
- fixed all CHK2/CMP2 instructions to support signed bounds. Previously it only worked with unsigned. Also sped up a bit
by changing | by || in Z evaluation formula
- cptrapcc opcodes are still unsupported, but if no exception occurs, at least PC is properly updated
- trapt/trapcc 16 & 32 instructions: PC is updated before exception is triggered (or if exception isn't triggered). This fixes the
return address value (just in case code returns from trap with RTE) and also the stackframe (XDAda 68040 compiler
read the data parameter to check exception type, wrong exception type is read if stackframe is incorrect)
in m68kfpu.c
- fatalerror message fprintf => vfprintf
- added address register + displacement mode (mode 5, READ_EA_FPE/WRITE_EA_FPE), also changed prototype to it can be called with this mode
from FMOVEM loop
- added immediate mode (READ_EA_FPE)
- fpgen_rm_reg (FMOVE to register): added a lot of missing condition code update (SET_CONDITION_CODES(REG_FP[dst]))
- added FSDIVS and FSMULS (easy as it's the same case as FDIV and FMUL). Updated condition codes for FDIV
- fmove_fpcr: connected softfloat 4 rounding modes to this instruction, that didn't set rounding at all, when it's
perfectly emulated in softfloat module (just added: float_rounding_mode = (REG_FPCR >> 4) & 0x3;)
- fmovem: added address register+displacement mode (READ_EA_FPE/WRITE_EA_FPE interface had to be changed)
- added FScc instruction
- note: number of cycles for the added instructions isn't exact
- fixed all CHK2/CMP2 instructions to support signed bounds. Previously it only worked with unsigned. Also sped up a bit
by changing | by || in Z evaluation formula
- cptrapcc opcodes are still unsupported, but if no exception occurs, at least PC is properly updated
- trapt/trapcc 16 & 32 instructions: PC is updated before exception is triggered (or if exception isn't triggered). This fixes the
return address value (just in case code returns from trap with RTE) and also the stackframe (XDAda 68040 compiler
read the data parameter to check exception type, wrong exception type is read if stackframe is incorrect)
m68kfpu.c:
- fatalerror message fprintf => vfprintf
- added address register + displacement mode (mode 5, READ_EA_FPE/WRITE_EA_FPE), also changed prototype to it can be called with this mode
from FMOVEM loop
- added immediate mode (READ_EA_FPE)
- fpgen_rm_reg (FMOVE to register): added a lot of missing condition code update (SET_CONDITION_CODES(REG_FP[dst]))
- added FSDIVS and FSMULS (easy as it's the same case as FDIV and FMUL). Updated condition codes for FDIV
- fmove_fpcr: connected softfloat 4 rounding modes to this instruction, that didn't set rounding at all, when it's
perfectly emulated in softfloat module (just added: float_rounding_mode = (REG_FPCR >> 4) & 0x3;)
- fmovem: added address register+displacement mode (READ_EA_FPE/WRITE_EA_FPE interface had to be changed)
- added FScc instruction
- note: number of cycles for the added instructions isn't exact
- BCD packed decimal now supported, including k-factor
- Improved FSAVE/FRESTORE including FPU reset when restoring a NULL frame
- FREM instruction supported
- Better disassembly of FPU instructions
- Rewritten to use SoftFloat instead of unportable native FP math
- Support added for Motorola 96-bit extended floats
- More addressing modes and conditions supported
The taitojc games function identically to the old implementation (I stepped
through the main matrix multiply in dendeg and the registers never diverged)
and speed on Core 2 Duo is a wash - sometimes softfloat's faster, sometimes
not, but the difference on -str 90 never exceeded 1%.
m68kmmu.h uses functions from m68kfpu.c which are static, so m68kfpu.c
can't be compiled alone anymore if we want to keep some basic
compatibility... I know, it's not super clean, but it's not my
choice...!
Also pmmu_translate_addr can't be inline anymore because of this (there
are quite a few functions from m68kcpu.h using it, and it can be
included only in m68kcpu.c !)
- Reworked PMMU/core interface so PMMU now sees all cop 0 instructions
- Improved disassembly of PMMU instructions
- Preliminary 68LC040 support
- Fixed disassembly for EC/LC variants of '030/'040
