Sets LinkServer as the default runner for the mimxrt1180-evk board,
as the board is configured for CMSIS-DAP by default.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
The on-board S26HS512T 512M-bit HyperFlash memory is connected to
the QSPI controller port A1.
This board configuration selects it as the default flash controller.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Create common source code to use for supporting HyperFlash.
Rename 'FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME' to
'FLASH_NXP_S32_QSPI_SFDP_RUNTIME' as a common kconfig.
Add the 'max-program-buffer-size' property to use for
setting memory pageSize, instead of using
'CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE' for setting.
Add the 'write-block-size' propertyto use for setting
the number of bytes used in write operations, it also
uses to instead of the 'memory-alignment' property.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Add comment to DTS file about SRAM partitions similar to the RTXXX
series has comments.
Add also a doc section to the frdm_rw612 about this.
Also fix the section hierarchy of the frdm_rw612 doc, the header levels
were wrong since the wifi and bluetooth, and reference sections were
under the debugging section.
Group all the wireless connectivity info together.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add support PWM eMIOS for s32z2xxdc2 board. There is no LED
on-board dedicated for PWM, so no sample is supported. Only
enabling some pwm tests
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Removing period, duty and polarity configuration from
channel devicetree. At boot time, only minimal setup like
pinctrl, prescaler, etc should be initialized. PWM signal
is produced by using pwm_set* API
Also after this change, PWM period, duty are changed at the
next counter period boundary
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
This commit removes all references to the `xtools` toolchain variant in the
board YAML files.
Note that the `xtools` toolchain variant has been deprecated since Zephyr
v3.3.0 and now removed.
The removal process was automated using the following command line:
git grep -l xtools -- boards/*.{yml,yaml} | \
xargs -n 1 -P $(nproc) \
yq -i 'del(.toolchain[] | select(. == "xtools"))'
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
10/100 ENET and gigabit ENET1G are supported on the EVKB revision.
Correcting the Supported Features table.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Change the property names in the bindings and DTS
to use hyphens(-) for separation instead of underscores(_).
Signed-off-by: James Roy <rruuaanng@outlook.com>
This commit adds multicore support for MCXN947.
It enables the secondary core CPU1 to boot from flash.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Enabling `CONFIG_INPUT_FT5336_INTERRUPT` if the ft5336 node in DT
has `int-gpios` property.
As a result of this change, some boards can eliminate lines that
explicitly configure `CONFIG_INPUT_FT5336_INTERRUPT`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add pinctrl and dma channel/mux information for lpspi3 on cm33/cm7 cores.
Set dma4 status is OK.
Add pinctrl for lpuart3
tests: driver: spi: support spi_loopback case on MIMXRT1180_EVK
Add .config/.overlay files for cm33/cm7 cores
Link to ocram1 as RAM region on cm7 core
Link to dtcm as RAM region on cm33 core
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
OCRAM region in Cortex-M4 memory map at 0x2020_0000 is simply an alias
to the M4 TCM at 0x1FFE_0000, which the zephyr,flash node was previously
set to. Using this base address for OCRAM allows the base address to
match the one used in the M7 memory map, which simplifies loading the M4
image from flash into RAM in the M7 init routine
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
There are 4 Kconfig names about the "Draw Buffer". Rename 'VBD' to 'VDB'
in Kconfig option 'LV_Z_*VBD*_CUSTOM_SECTION' to make name consistent.
config LV_Z_VDB_ALIGN
int "Rending buffer alignment"
config LV_Z_VBD_CUSTOM_SECTION
bool "Link rendering buffers to custom section"
config LV_Z_DOUBLE_VDB
bool "Use two rendering buffers"
config LV_Z_VDB_SIZE
int "Rendering buffer size"
default 100 if LV_Z_FULL_REFRESH
And the draw buffer definition is now:
static uint8_t buf0[BUFFER_SIZE]
#ifdef CONFIG_LV_Z_VDB_CUSTOM_SECTION
Z_GENERIC_SECTION(.lvgl_buf)
#endif
__aligned(CONFIG_LV_Z_VDB_ALIGN);
Signed-off-by: Haiyue Wang <haiyuewa@163.com>
- Enables a MCUboot support for frdm-mcxa156.
- Enables MCUMgr OTA and MCUBoot recovery for frdm-mcxa156.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Convert qspi and hyperflash to variants instead of revisions by popular
demand.
And convert evkb into a revision instead of a different board.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Rename "nxp,kinetis-ftm-pwm" compatible to "nxp,ftm-pwm" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Creation of the new zephyr\soc\nxp\common\nxp_nbu.c driver which manage
the interruption of the NBU. This modification is mandatory to support a
coex application which includes Bluetooth and 802.15.4 on the same
narrow band path.
Signed-off-by: Xavier Razavet <xavier.razavet@nxp.com>
add the i3c2 pin setting
set i3c2 instance as ok status
add p3t1755dp_ard_i3c_interface/p3t1755dp_ard_i2c_interface node label
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
imx8qm and imx8qxp have a couple of differences regarding
the peripheral address spaces and how the DT nodes are
configured, which is why using a generic DTSI (nxp_imx8.dtsi)
for the both of them is not right.
One of the differences between the two, which affects Zephyr
is the fact that irqstr's address space is different. Up until
now this has been dealt with at the board level (i.e:
imx8qxp_mek_mimx8qx6_adsp.dts), which is not right as this is not
board-specific, but rather soc-specific. Additionally, this
causes the following warning during compilation:
"unit address and first address in 'reg' (0x51080000) don't
match for /interrupt-controller@510a0000"
To fix this, add two new DTSIs: nxp_imx8qm and nxp_imx8qxp.
Each board (i.e: imx8qm_mek and imx8qxp_mek) will have to include
the DTSI for their soc instead of the generic DTSI (i.e: nxp_imx8).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
