Add shield definition for the Mikroe ETH 3 Click.
ETH 3 Click is a compact add-on board that contains
LAN9250 SPI Ethernet Controller
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Add support for UDC on highspeed port on these boards:
- ek_ra8m1
- ek_ra8d1
- ek_ra6m5
- ek_ra6m3
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Improve Simics support for `boards/intel/ish/intel_ish_5_8_0`
for better integration with the simulator.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
This is the initial commit to support pinctrl driver for Renesas RZ/G3S
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This adds minimal support for board RZ/G3S-SMARC
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
This commit enables I3C support for STM32 nucleo_h563zi boards.
Signed-off-by: Mohammad Badawi <zephyr@exalt.ps>
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
Due to Apollo3's internal bootloader, zephyr build is not able
to create correct flash address on linker.cmd while using
mcuboot. The PR configures flash-controller start address
to solve this problem.
Test board: rakwireless/rak11720
Test project: samples/subsys/mgmt/mcumgr/smp_svr
Signed-off-by: Sercan Erat <sercanerat@gmail.com>
Configure the TE signal for the rw_rw612_bga board when using the
lcd_par_s035 shield. This signal should be handled on the rising edge in
the default configuration, since the display writes from the MCU are
faster than the panel reads data.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This board has the required clock crystal (X4) and jumper settings
present to enable the USB 2.0 HS support.
* Enable the HSE clock (16MHz)
* Flip the PLL1 configuration over to use the HSE clock, but still
outputting 160MHz to sysclk/apbclk.
* Add the USB HS device tree node.
* Update the board documentation.
Signed-off-by: Adrian Chadd <adrian.chadd@meta.com>
Configure the Raspberry Pi Pico W for WiFi.
Move Pico W configuration details to devicetree
Add pinctrl configurations for data/interrupt sharing
Make memory config selectable
Align devicetree with Linux ordering
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
- Add support CAN-FD for EK-RA6E2, EK-RA4E2
- Enable ioport for can-transceiver on EK-RA6E2, EK-RA4E2
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
ENTROPY_GENERATOR is now automatically enabled if the board
has "zephyr,entropy" chosen property set, so there is no need
to manually select it.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Add the required code for `west debug` to work the FLPR
core over JLink in the nRF54L 05, 10 and 15 devices.
Note that this requries an external J-Link probe, it will not work with
the on-board (OB) probe soldered on the DK.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add entropy support for these boards: ek_ra6m1, ek_ra6m2, ek_ra6m3
Signed-off-by: Danh Doan <danh.doan.ue@bp.renesas.com>
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
drivers/input/input_gpio_keys.c requires property "zephyr,code" must
be provides for gpio-keys, so add code property for imx93_evk A55
and M33 boards.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Correct "zephyr,sram" property under /chosen node to make board and samples
compatible with new SoC memory description.
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
This option gets the default value "y" whenever HAS_BT_CTLR is enabled, and
since the EFR32 HCI driver now selects HAS_BT_CTLR the right thing happens
either way.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
During migration to HWMv2 separate specific defconfig file was removed
for GICv3 version of virtual xenvm boards. It worked fine before
commit 0be0d2175b ("cmake: modules: extensions: Revert using common
board files") significantly changed build behavior, but did not return
previously removed file. This led to build/runtime issues, when some of
the Kconfig options were not selected.
Return GICv3 specific defconfig to board directory to fix configuration
problems.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
This makes minichlink the default runner for the ch32v003evt.
This way, `west flash` "just works", as advertised in the README, rather
than having to manually set the runner to `minichlink` for it to work.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The PINCTRL option is selected now by the drivers which use it, so
it's possible to remove it from the board defconfig.
Signed-off-by: Ilya Tagunov <Ilya.Tagunov@synopsys.com>
Enable i2c and configure it to read accelerometer sensor on the board.
Test it using sample.sensor.accel_polling.
Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
xenvm Kconfig contained incorrect name for board parameter. It led to
build issues - heap size was set incorrectly. Since whole file is
already placed under right Kconfig condition ("if BOARD_XENVM"), remove
incorrect parameter at all.
This issue was introduced by commit 8dc3f85622 ("hwmv2: Introduce
Hardware model version 2 and convert devices") due to the typo.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
Added basic support for west debug for nrf54h20
RISC-V cpus: nrf54h20_cpuppr and nrf54h20_cpuppr.
Note external jlink probe needs to be used.
Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
This boards was merged before rp2040.dtsi changed location.
Update the include in its dts file accordingly
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Change whitespace to match the coding style for CMake files for all
rp2040-based boards.
This is foundation work ahead of adding support for boards based on the
RP235XX SoCs.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
No in-tree board uses this driver's pinctrl functionality, and every
RP2040-based board was configuring this to be an empty node in the
device tree, so remove them.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Follow the wider directory convention of dts/<arch>/<vendor>/<family>.
This is foundation work ahead of introducing support for the RP2350.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Enable Ethernet controller node and mdio node for RA boards.
Add pinctl for mdio and Ethernet usage
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
mcxc444 also has pit and rtc counters, add the counters to
board documentation, and enable it explicitly in board dts.
Set rtc clock to 32 kHz oscillator.
Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
Add support for Norik Systems Octopus IO-Board based on
Norik Systems Octopus SoM.
Supported features:
- LTE-M/NB-IoT
- GPS
- LED
- 3-axis accelerometer
- Battery charger
- Solar charger
- SPI NOR flash
- Nano SIM connector
Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
Add support for Norik Systems Octopus SoM based on nRF9160 SiP.
Supported features:
- LTE-M/NB-IoT
- GPS
- LED
- 3-axis accelerometer
Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
For Zephyr Cortex-A Core supports on NXP boards imx8mm, imx8mn, imx8mp,
imx93 and imx95, currently use DDR DRAM memory as Zephyr memory, so
change RAM dts nodes name to be "dram" in order to reduce confusion.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
- Adds 'supported: flash' to all NXP board .yaml
with enabled flash controller support.
- Sorts supported features alphabetically.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Add `se` variant to support the low-cost CoreS3 SE.
- Add configuration files
Add `m5stack_cores3_procpu_se(.dts|.yaml|defconfig)` files.
Reorganize dts files to split common parts.
- Update .yaml file
Add gpio, can, counter, entropy, pwm, and pinmux to the supported
feature group. Remove the `ignore_tags:` section.
- Update documents
Add and modify information about CoreS3 SE.
Add more description about sysbuild.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Enable the cpusec IPC and the bellboard nodes for
the nrf54h20dk cpuapp and cpurad targets to enable
communication between domains.
Also enables the region cpurad_ram0x_region since
it is also required for the communication.
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
Deprecate BT_CTLR, and add a new HAS_BT_CTLR as a virtual option which
specific users (like BT_LL_SW_SPLIT) select. This also means that we can
remove all places that were forcefully enabling the BT_CTLR option, and
instead we now depend on devicetree to get some local LL HCI driver
enabled which in turn also enables the HAS_BT_CTLR option.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Change running baudrate from `115200` from `3000000`.
Implement the function `bt_h4_vnd_setup` to update the HCI bandrate.
Add Kconfig `BT_H4_NXP_CTLR_WAIT_TIME_AFTER_BAUDRATE_UPDATE` to set
the waiting time after the controller bandrate HCI vendor specific
command sent. It is used to ensure the controller is ready to update
HCI bandrate.
Select `BT_HCI_SETUP` if `BT_H4_NXP_CTLR` is enabled.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
The nRF54L15 DK can now be used to emulate its lesser siblings, the L05
and the L10. Document this in the board reference so that user are aware
of this fact.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Gap filling in hex files are now disabled per default, and therefore
there is no reason to explicitly disable gap filling.
It has never been possible to disable gap filling in binary files.
Disabling gap filling would just result in the binary file to be gap
filled with the tool's default value, objcopy=0x00.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
The mechanism for communication between domains requires
extra threads. So change the default value MAX_THREAD_BYTES
to allow usage of more threads.
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
Add uart-pipe driver default option in device trees for silabs boards.
It enables vcom for the boards, handy to have for sample application, for
example tester app.
Signed-off-by: Evgenii Kosenko <Evgenii.Kosenko@silabs.com>
Add 128 MHz clock source and use it for uart00. Baudrate setting
must be adjusted based on uart clock source so without this
change there is wrong baudrate on uart00.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add Zephyr support for the Audio DSP on the MT8196 SOC. This is a
very similar device to previous designs. Most of this patch is just
DTS.
The biggest delta is the more complicated second level interrupt
controller, though it is still able to be represented using some
vaguely clever DTS config over the older intc_mtk_adsp driver.
Also the memory layout is slightly different, requiring a little
indirection to set the initial boot stack address and log output
buffer. And the timer "irq_ack" register bits moved.
Signed-off-by: Andy Ross <andyross@google.com>
Add a twister YAML file for these devices. Right now they're flagged
as xt-clang only, though xcc and SOF-derived gcc toolchains are known
to work too. We'll enable the zephyr SDK once sdk-ng support lands.
Signed-off-by: Andy Ross <andyross@google.com>
These are very similar devices to mt8195, minimal changes needed
beyond boilerplate configuration.
In the process, this reworks the board/soc layout to be HWMv2
compliant, with "adsp" becoming a CPU cluster beneath the SOC. So the
name of the boards to west become e.g. "mt8195/mt8195/adsp" (which can
be shortened to "mt8195//adsp" if desired).
Note that the cpuclk driver is not yet ported, it works only with 8195
(the clocking/power architecture seems similar between the parts, but
the graph of wells and clocks is different and historically these have
been three separate drivers in SOF). The biggest changes are in the
image/loader scripts, which needed some rework for cross-device
portability.
Signed-off-by: Andy Ross <andyross@google.com>
This board is mostly the same as mini_stm32h743.
Noatable diffrences for dt:
- rcc config
- octospi in quadspi mode
- pinmux naming for USB and quadspi
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
Added ability for host MCU to perform a hardware reset of the DA14531
contained on the Mikroe BLE Tiny Click.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
There is a mistake and the cpuapp_ram0x_region "reg" value should
start from 0x2f011000.
Signed-off-by: Arkadiusz Balys <arkadiusz.balys@nordicsemi.no>
The GECKO_PIN() macro does not do anything except pass the
argument through unaltered. It only serves to make DeviceTree
files more verbose. It was inconsistently used, make the .dts
files consistent by never using it.
The DBUS pinctrl driver doesn't use the port or location macros
from the gpio_gecko.h header. The pin number macro is the only
other thing defined in this header. Stop including the header on
Series 2 based boards.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Swap from silabs,gecko-pinctrl to silabs,dbus-pinctrl for all boards
with Series 2 SoCs. Explicitly declare pin properties as part of
pinctrl pinout configuration.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
BT uses PSA Crypto API to perform crypto operations and, on this
platform, these APIs are implemented through Mbed TLS. In order
to properly initialize this library, a random number generator
is required.
* If the platform supports an HW entropy generator (ex: native_sim,
nrf), then ENTROPY_GENERATOR must be used;
* Otherwise (ex: qemu_cortex_m3) test random generator can be
enabled.
Enabling the proper option at board Kconfig level allows for
a more compact code change instead of manually editing _all_
the samples/tests that required this fix.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
- Fixes MCUBoot build error when enabled Serial Recovery via USB CDC ACM.
- Increases MCUBoot partition size.
Signed-off-by: Andrej Butok <Andrey.Butok@nxp.com>
BUS_5V regulator is placed in the i2c peripheral, where it does
not belong. Move 5V bus regulator to board common definitions.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The #81456 fixed the driver issue related to issue #81454. This add
the RTC configurations on sam_v71_xult board to enable test coverage.
Fixes#81454
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Per the docs, the memory at address 0x80000000 ends at 0xC0000000.
In other words, the address space is 0x40000000, which is only half
of the size we want to map. This means that the upper address space
previously mapped was overlapping with the space reserved for non-cached
memory.
Instead, we map the entire 2GB at 0x1000000000, which is the correct
address for cached DDR that occupies more than 1 GB.
We defined a new node in the device tree for this memory region,
`beaglev.ddr_cached_high`. We did not reuse the `soc` node because
we needed to redefine the `#address-cells` to be 2, and doing so
would have affected other nodes under `soc`.
Signed-off-by: Alex Charlton <alex.n.charlton@gmail.com>
uart1 is not connected to anything as far as I can tell.
uart0 was the previous correctly selected uart, so this changes
back to that.
Signed-off-by: Alex Charlton <alex.n.charlton@gmail.com>
- Trace32 runner: no need to configure TE bit in CFG_CORE
register in the cmm start-up script, it can be configured
at Zephyr start-up code when required (via SCTRL register)
- MPU static regions also needs to be updated for XIP and
non-XIP
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Add devicetree node for code RAM, code RAM can be accessed
over AIXM bus or AXIF bus. Code access via AXIF interface
provides the best optimal performance
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
This commit adds a runner wrapper for the 'minichlink' program which
offers a free, open mechanism to use the CH-LinkE programming dongle for
the CH32V003.
https://github.com/cnlohr/ch32v003fun/tree/master/minichlink
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This commit adds support for the CH32V003EVT board which features a
32-bit general-purpose RISC-V MCU.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
The ram0x partitions seem to be not compliant with nRF54H20
architecture and it causes that in the application dts overlay file
it is difficult to extend cpuapp_ram0x_region without modifying
whole layout.
It is better to place cpurad_ram0x_region at the beginning at
2f010000 address and then cpuapp_ram0x_region right after that.
Thanks to that, if the application needs to have more than 256 kB
of RAM, in the application dts overlay file, a user can increase
cpuapp_ram0x_region size up to 2f0be000.
Signed-off-by: Arkadiusz Balys <arkadiusz.balys@nordicsemi.no>
Add missing "pinctrl-names" and "status" properties for
the spi1 node in ek_ra8m1.dts to able to test spi_loopback
on ek_ra8m1
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
The B_L4S5I_IOT01A Discovery kit does not boot up when using --sysbuild.
The error is caused by slot0_partition which is assigned an address of
0x1000 which overlaps with the boot_partition. Setting the address to
0x10000 fixed it.
Signed-off-by: Winston Arrocena <we.arrocena@gmail.com>
Added mikrobus_header, mikrobus_i2c, mikrobus_spi and mikrobus_serial
node labels to da14695_dk_usb device tree board definition, allowing
compatible shield boards to be used. Also fixed minor issues with
pin assignment and header labelling.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Enable BLE feature for Nucleo-WB09KE and Nucleo-WB05KZ.
Dedicate 32KB and 8KB at the end of flash memory to storage partition on
Nucleo-WB09KE and Nucleo-WB05KZ respectively.
Add ble tag to the both devices yaml file.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
`_current` is now functionally equals to `arch_curr_thread()`, remove
its usage in-tree and deprecate it instead of removing it outright,
as it has been with us since forever.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Use a string for the mipi-mode property over an integer value, as this
significantly improves the readability of the MIPI DBI device binding.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The NXP LCDIC peripheral contains two internal timers, with configurable
periods. These times are used to determine delays within the peripheral,
such as the reset and tearing enable signal delays. Allow these periods
to be set within the devicetree for the peripheral.
Raise the period where required for display drivers that need a value
other than the reset setting
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add note about compatible change for NXP PORT IP. Also, update
references to the DT compatible within board docs.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
* Replace copies of fixed-partitions nodes in related boards by
referencing the apropriate partition table from the available list.
* For better reference the `partitions_*.dtsi` file has boot offset,
purpose and the flash size encoded in the file name. Default flash size
is considered to be 4MB.
* Added the flash size node for the boards which are not based on the
module.
* Removed flash size registry from the esp32.*common.dtsi
Signed-off-by: Marek Matej <marek.matej@espressif.com>
STM32F4 series flash layout is as follows:
{.pages_count = 4, .pages_size = KB(16)},
{.pages_count = 1, .pages_size = KB(64)},
{.pages_count = 7, .pages_size = KB(128)}
Since NVS subsys requires 2 sectors of max 32K in total, provide a
flash partition which respects this constraint using 2 of the 16K sectors
in the beginning of the layout.
Provide a compatible flash partition usable with mcuboot, but keep the
storage partition commented as its usage is not compatible with use w/o
mcuboot enabled (in this case main image starts as offset 0 which conflicts
with storage partition).
Note that it isn't possible either to get main image starting directly
in the 128K sectors w/o bootloader as boot flash address can't be
configured.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
NVS susbsystem requires a slot covering 2 sectors of flash, which
should be at minimum 8K on L1 series which provides 4K sectors.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
NVS susbsystem requires a slot covering 2 sectors of flash, which
should be at minimum 4K on G0 series which provised 2K sectors.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
STM32F2 series flash layout is as follows:
{.pages_count = 4, .pages_size = KB(16)},
{.pages_count = 1, .pages_size = KB(64)},
{.pages_count = 7, .pages_size = KB(128)}
Since NVS subsys requires 2 sectors of max 32K in total, provide a
flash partition which respects this constraint using 2 of the 16K sectors
in the beginning of the layout.
Provide a compatible flash partition usable with mcuboot, but keep the
storage partition commented as its usage is not compatible with use w/o
mcuboot enabled (in this case main image starts as offset 0 which conflicts
with storage partition).
Note that it isn't possible either to get main image starting directly
in the 128K sectors w/o bootloader as boot flash address can't be
configured.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Align the total SRAM size for STM32L47x/L48x/L49x/L4Ax
boards. Those MCUs with up to 320 Kbytes SRAM:
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Align the total SRAM size for STM32L47x/L48x/L49x/L4Ax
boards. Those MCUs with up to 320 Kbytes SRAM:
• 96 Kbytes SRAM1 and 32 Kbyte SRAM2 on STM32L47x/L48x.
• 256 Kbyte SRAM1 and 64 Kbyte SRAM2 on STM32L49x/L4Ax
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The board shares many features with other Arduinos based on STM32H747
(like the HSE in bypass mode).
Once https://github.com/zephyrproject-rtos/zephyr/pull/76542 is merged,
PF1550 support should be added too to allow switching IO voltage
from 3v3 to 1v8
Signed-off-by: Martino Facchin <m.facchin@arduino.cc>
Right now, USART1 is enabled on the M7 target variant by default, leaving
M4 without a UART to use; this is the way this port was originally
contributed.
Since then, USB was enabled on M7, changing the console backend from USART1
to USB CDC ACM; the M4 target was left unchanged.
This commit enabled USART1 on the M4 variant and disabled it on the M7
variant, so that the M4 variant can use it as its console backend.
Note that, for the M4 variant, USART1 has been assigned to `zephyr,console`
and `zephyr,shell-uart` since this port was contributed, even though USART1
was always disabled on M4.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Include in the list of supported peripherals the UARTE for the
simulated nrf54l15
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The HW models now support this peripheral for this target.
Let's enable it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The nRF54L05 and nRF54L10 are identical to the nRF54L15 except for their
memory sizes. Add support for emulating those ICs on the nRF54L15DK.
This commit only adds support for the main application core. Support for
the FLPR core may be added later.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Use the rather logical convention for the name that is applied to other
Nordic boards: <board>_common.dtsi for definitions that are common to
the board itself (LEDs, buttons, etc).
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
device tree:
enable support for the SDHC controller to use the micro SD card slot
documentation:
- added instructions for SD card and OLED samples
- added links to code samples
defconfig:
added CONFIG_ESP32_USE_UNSUPPORTED_REVISION=y to
ttgo_lora32_esp32_procpu_defconfig
The chip on the board is a ESP32 chip revision 1.
The board will not boot, it displays the following warning at boot:
I (35) boot: chip revision: v1.0
E (38) boot: You are using ESP32 chip revision (1) that is unsupported.
While it may work, it could cause unexpected behavior or issues.
E (50) boot: Proceeding with this ESP32 chip revision is not recommended
unless you fully understand the potential risk and limitations.
E (62) boot: If you choose to continue, please enable the
'CONFIG_ESP32_USE_UNSUPPORTED_REVISION' in your project configuration.
E (73) boot: HW init failed, aborting
In order to prevent a boot loop, CONFIG_ESP32_USE_UNSUPPORTED_REVISION=y
was added to the defconfig.
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
Use configdefault when enabling LV_COLOR_SWAP_16 within boards and
shield definitions, to avoid OR'ing the dependencies for the Kconfig
symbol. Otherwise, a user manually selecting LV_COLOR_DEPTH will
encounter build errors as LV_COLOR_SWAP_16 may be enabled when
LV_COLOR_DEPTH_16 is not selected
Fixes#81546
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
USE_HYPERRAM macro defined shouldn't be placed under
CONFIG_BOOT_FLEXSPI_NOR.
Add flexspi1 pinmux pinctrl and flash partitions
Add flash partitions and correct flash parameter.
This commit was tested with samples: flash_shell on cm33/cm7 cores
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
A valid device tree configuration is provided for the ADCs of the 8 input
channels and the sample adc_dt works out of the box. Obviously this is
not the only possible configuration but it provides a good template for
further customization without the need to lookup the ADC GPIOs and
connections in the schematics.
Signed-off-by: Federico Di Gregorio <fog@dndg.it>
This set of changes enables the RS485 hardware connected to usart3 and
provides some overlays that allow for easily running the modbus
rtu_client and rtu_server samples on Opta.
Signed-off-by: Federico Di Gregorio <fog@dndg.it>
Some changes to cleanup and clarify some device tree nodes:
* removed wrong sdram2 definition
* added all internal flash slots accessible from M4
* added all internal flash slots accessible from M7
* removed CONFIG_UART_LINE_CTRL because not needed by USB CDC ACM
Signed-off-by: Federico Di Gregorio <fog@dndg.it>
This set of changes reorganize the ethernet configuration by removing the
use a regulator to enable the PHY: the correct GPIO pin is set in code
only if the network has been configured via CONFIG_NET_L2_ETHERNET.
Signed-off-by: Federico Di Gregorio <fog@dndg.it>
The prior image was of poor quality, making it difficult to interpret.
Updated the image with a higher-quality version.
Signed-off-by: Dhruv Menon <dhruvmenon1104@gmail.com>
To remove CONFIG_PINCTRL from board side for numaker boards.
The Drivers using Pinctrl should be turning Pinctrl on
instead of the responsibility of the board.
Fixes#78619
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Add `hifive_unmatched//s7` (earlier selected by default, using
`hifive_unmatched`) and `hifive_unmatched//u74` targets.
Define work-area for other 4 cores in openocd.cfg
Update twister platform white/black lists, to support new targets
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Add `hifive_unleashed//e51` (earlier selected by default, using
`hifive_unleashed`) and `hifive_unleashed//u54` targets.
Define work-area for other 4 cores in openocd.cfg
Update twister platform white/black lists, to support new targets
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Switch from `ram0` to `l2lim` in `zephyr, sram` in board DTS
Add `l2lim` in `support/hifive_unleashed.resc` and targets l2lim
as a work-area in `openocd_hifive_unleashed.cfg`
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This option existed only to make the transition from native_posix to
native_sim easier. As native_posix is going to be removed in v4.2
we deprecate this option now, so it will also be removed.
We also switch this option to default to false already now.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This board has a few issues handled by this PR:
- Fix DTS entries to meet necessary flash partitions
- Fix wrong kconfig entries realted to SoC model
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add UART configuration and pin control. Set state to disabled,
as it serves as alternative to default LPUART0 or as second
uart only.
Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
Add CONFIG_GPIO from defconfigs for Infineon boards.
Revert pull/81377, which affect some ble samples which
used GPIO.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
This commit changes the way some x86 devicetree set the unit-address values
of memory nodes. Before the change, they were always set to `0`. After the
change, they are derived from the `DT_DRAM_BASE` macro to match the first
address specified by the reg property.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Zephyr SDK 0.17.0 adds the toolchain for the Intel Audio DSP
ACE 3.0 platforms. We can now add the bits to enable building
the boards with SDK 0.17.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The patch modifies the "Programming and Debugging" and "Flashing" sections
to make the documentation clearer and consistent with what is reported for
other ST boards.
Suggested-by: Abderrahmane Jarmouni <git@jarmouni.me>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
The building and flashing of the drivers/display and subsys/display/lvgl
examples confirmed that the LTDC peripheral is supported.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
The commit e17e54c48f ("boards: stm32: add flashing with stm32cubeprog
for all") did not update the documentation regarding the flashing
section, which no longer uses the OpenOCD runner by default.
Fixes: e17e54c48f
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
This commit defines the default pinctrl of ITM for Apollo3 and
Apollo4 EVB. Also configures the default SWO frequency.
Signed-off-by: Aaron Ye <aye@ambiq.com>
- Refactoring of the cmake code so LinkServer can be invoked with the
correct switches.
- Documentation update
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Openocd target cyw20829 does not define _TARGETNAME which is used by
default by the openocd west runner when using CONFIG_DEBUG_THREAD_INFO.
This is similar to the issue previously addressed for STM32H7:
Link: https://github.com/zephyrproject-rtos/zephyr/issues/45778
Signed-off-by: Hakan Jansson <hakan.jansson@infineon.com>
Add MAX78002EVKIT board.
For more information about this board please check
https://www.analog.com/
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
The nRF54H20 Development Kit version 0.8.0 is no longer supported, given
that they should have all been replaced by 0.9.x.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Added pmod_serial and pmod_header node labels to EK-RA8M1 device
tree board definition, allowing compatible shield boards to be used.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Add USB node to apollo4p and apollo4p_blue qualifier, and apollo4p_evb
and apollo4p_blue_kxr_evb board to enableUSB support on the MCU and
its EVB.
Signed-off-by: Chew Zeh Yang <zeon.chew@ambiq.com>
Include in the list of supported peripherals the UARTE for the
simulated nrf5340
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The HW models now support this peripheral for these targets.
Let's enable them.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Include in the list of supported peripherals the GPIO
and GPIOT for both the nrf5340 and nrf54l15
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This will help distinguish 64 and 32-bit platforms by tooling, following
the pattern visible in e.g. RISC-V.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
atom.dtsi enforces "intel,x86", but it doesn't help us discern if the
platform is 32 or 64-bit. We do that for example in RISC-V and it's
useful from the tooling perspective.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
Add definition for the Adafruit Adalogger Featherwing. This shield
compatible with the Adafruit Feather family is equipped with an SD card
slot and a PCF8524 RTC.
This work is based on the Adafruit Data Logger shield definition.
Signed-off-by: Philip-Dylan Gleonec <philip-dylan@gleonec.bzh>
Initial support for M5Statck CoreS3 development board.
Signed-off-by: Zhang Xingtao <zhxt@live.cn>
Co-authored-by: Benjamin Cabé <kartben@gmail.com>
Co-authored-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The Adafruit Feather M4 Express is a compact, lightweight
ARM development board with an onboard mini NeoPixel, 2 MiB
of SPI flash, charging status indicator and user LEDs, USB
connector, 21 GPIO pins and a small prototyping area.
Signed-off-by: Teresa Zepeda Ventura <teresa.zvent@gmail.com>
ST ZIO connector is Arduino Uno compatible. Arduino SPI pins are placed on
D10-D13 pins, where D10 is SPI nCS pin. This pin is connected with PD14 of
STM32U5A.
According to schematics of this Nucleo board [1]:
Due to muxing constrainte, the SPI_NSS is not available as an alternate
on this IO, so this pin is affected with an I/O function to do the Chip
Select
This means that software control of GPIO is needed to make use of this SPI
interface on regular SPI signals on Arduino connector. Reconfigure
SPI1 (used as Arduino SPI) interface to account for that.
Note that previously configured PE12 is only available on ST ZIO and ST
Morpho connectors, not on Arduino connector.
Update documentation as well, which was referencing PA4 as nCS signal (used
on some other Nucleo boards).
[1] https://www.st.com/resource/en/schematic_pack/mb1549-u5a5ziq-c04-schematic.pdf
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
- Sets s26ks512s0 flash write-block-size to correct 256KB.
- Optimizes MCUboot partitions to fit the correct write-block-size.
Fixes#80284
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Clarify that one can simulate equally well the nRF54L10 and L05
variants with this target.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This target simulated is reasonably tested.
Let's stop warning about it being experimental.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Fix compilation error by specifying usart1 to be used for uart-pipe.
Add a board-specific configuration file to disable the console,
so, the usart1 will be used only for bluetooth and to specify
the BT_HCI_TX_STACK_SIZE.
Signed-off-by: Nidhal BEN OTHMEN <nidhal.benothmen@st.com>
Let's fix the sample used in the example. The peripheral_hr and
central_hr are meant to be run with each other.
Let's also use the :zephyr:code-sample: directive to refer to the
samples so we get a link.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
-Update formatting and contents of index.rst for cy8ckit_062s4
-Update formatting and contents of index.rst for cy8ckit_064s0s2_4343w
-Update formatting and contents of index.rst for cy8cproto_062_4343w
-Update formatting and contents of index.rst for cy8cproto_063_ble
-Update formatting and contents of index.rst for xmc45_relax_kit
-Update formatting and contents of index.rst for xmc47_relax_kit
-Change all instances of "PSoC" to "PSOC" for infineon platforms
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
Remove CONFIG_GPIO from defconfigs for Infineon boards.
Applications, drivers will enable GPIO if need.
Added 'select GPIO' from spi/Kconfig.ifx_cat1
Added 'select GPIO' from wifi/infineon/Kconfig.airoc
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Moved uatr6 to common dts for m4
- cm0 uses uart-5 in ver 0.0.0 and uart-5 in ver 1.0.0 (for
using of Arduino headers).
- cm4 by default uses uart-2 (for ver 0.0.0 and ver 1.0.0)
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
This updates the documentation of all the LilyGO boards to use
the new `zephyr:board::` directive.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Flash support for RT1170 EVKB was fixed with cfb7322107 (drivers: flash:
flash_mcux_flexspi: add support for W25Q512NW-IQ/IN). Document this
support in the board page.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Minimum heap pool should be always set for the board
in order to enable internal drivers/subsystems to work.
It is currently not defined for APPCPU due to typo in
board's Kconfig, possibly causing build failures.
Fixes#81218
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Fix missing flash and code partition.
Add missing dts entries and use common partition tables to all related
non-Espressif boards, previously ommited.
Add uart1 node in pinctrl for APPCPU.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
By default, libc malloc allocated area is using all available RAM.
For some yet unknown reason, this conflicts with TF-M resulting in a
Hard Fault before jumping in the non secure application.
For now, define a Libc malloc area defined to 2048 which is the default in
some other typical applications (ARMv7 targets enabling USERSPACE).
Fixes#77847
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Increase target DSI clock frequency for the RT1160, as the DSI
peripheral requires a faster clock to account for the DSI packets that
must be sent outside of video mode frames.
This fix was previously applied for the RT1170, but is also needed for
the RT1160 SOC as they use the same DSI IP.
Fixes#78299
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The CONFIG_PINCTRL is removed from the board's defconfig files.
Drivers which use pin control function should add "select PINCTRL"
in their Kconfig files.
Fixes#78619
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
mdio_enet_nxp driver accesses the registers of its parent node Ethernet MAC
This commit enables this node in mimxrt1062_fmurt6 board's device tree.
This also fixes Issue #80881
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Status and request GPIOs are missing from the edge connector, add those
to fix Thingy53 + nRF7002EB build.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Remove CONFIG_MMC_VOLUME_NAME, and set the disk name based on the
``disk-name`` property. This aligns with other disk drivers, and allows
for multiple instances of the mmc_subsys disk driver to be registered.
Add disk-name properties for all in tree definitions for the
mmc-subsys disk driver, and change all in tree usage of the disk name
Fixes#75004
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove CONFIG_SDMMC_VOLUME_NAME, and set the disk name based on the
``disk-name`` property. This aligns with other disk drivers, and allows
for multiple instances of the sdmmc_subsys disk driver to be registered.
Add disk-name properties for all in tree definitions for the
sdmmc-subsys disk driver, and change all in tree usage of the disk name
Fixes#75004
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
According to the datasheet, the PHY address is 0x1. When changed to this
value the PHY id is correctly read.
Before:
```
[00:00:00.602,000] <err> phy_mii: No PHY found at address 0
```
After:
```
[00:00:00.051,000] <inf> phy_mii: PHY (1) ID 7C111
```
Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
The new update of clock device tree make the pll p q r clock
source cannot be choose by other node
This fix add 1 new dts binding for pll out p q r out line
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
I recently found out, that the Ethernet support for the boards Nucleo
H563ZI and STM32H573I-DK is already available but it isn't mentioned
in the "Supported Features" section.
Signed-off-by: Philipp Steiner <philipp.steiner1987@gmail.com>
Let's explicitly mention we are enabling the native_posix entropy
driver for this board (the real nrf54l15dk does not have an entropy
driver in Zephyr yet).
And correct a bit the wording around mbedtls as for the real target we
don't have mbedtls with HW acceleration.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This causes a build error as nRF70 driver running on CPU APP needs this
when SR co-existence is enabled.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Missed a few keys while moving to the new style twister.yaml file for
the intel_adsp platform. Add those back.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
SOCs using ECC require the SEGGER RTT control block address to be
provided to the tooling, as the SEGGER tools will not scan the memory
range of ECC ram. Add documentation making this clear to boards with
these SOCs.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
