The exit latency and min residency is handled by sl_power_manager.
This improve power consumption by letting the device sleep longer.
Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
Add TI OMAP interprocessor mailbox nodes for AM62X M4,
the user ID assignment is as per thec corresponding mailbox
interrupt assignment for the core.
More details can be found in the device TRM Mailbox section:
https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Switch the default entropy driver for 54L05/10/15 devices to the new
CRACEN based one.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The enet2 node in nxp_rt1060.dtsi incorrectly references &enet_ptp_clock
for its nxp,ptp-clock property. This commit updates the reference to
&enet2_ptp_clock.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Add `#address-cells = <0>;` to interrupt provider nodes in
the NXP S32 device tree to resolve warnings: e.g.
Warning (interrupt_provider): /soc/interrupt-controller@47800000: Missing
Warning (interrupt_provider): /soc/siul2@40520000/eirq0@40520010: Missing
This ensures compliance with device tree specifications and
eliminates build warnings.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The on-board S26HS512T 512M-bit HyperFlash memory is connected to
the QSPI controller port A1.
This board configuration selects it as the default flash controller.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Add comment to DTS file about SRAM partitions similar to the RTXXX
series has comments.
Add also a doc section to the frdm_rw612 about this.
Also fix the section hierarchy of the frdm_rw612 doc, the header levels
were wrong since the wifi and bluetooth, and reference sections were
under the debugging section.
Group all the wireless connectivity info together.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add support for the Antmicro's Myra SiP Baseboard. The board uses
Antmicro's Myra SiP which integrates STM32G491XX MCU and its SoC
configuration.
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Add `smb-wui` property to support wake-up from sleep mode by START
condition when i2c is configured to target mode.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This adds support PWM EMIOS for NXP S32Z SoC, both PWM pulse
generate and pulse capture are supported
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Fixes the CMake Warning on build/zephyr/zephyr.dts:
Warning (spi_bus_bridge): /soc/xspi@47001400: node name
for SPI buses should be 'spi'
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes the CMake Warning on build/zephyr/zephyr.dts:
Warning (spi_bus_bridge): /soc/octospi@52005000: node name
for SPI buses should be 'spi'
<stdout>: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge'
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes the CMake Warning on build/zephyr/zephyr.dts:
Warning (spi_bus_bridge): /soc/octospi@52005000: node name
for SPI buses should be 'spi'
<stdout>: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge'
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add initial SoC support for the TI J722s SoC series MCU-domain
Cortex-R5 core.
TRM for J722s: https://www.ti.com/lit/zip/sprujb3
Signed-off-by: Andrew Davis <afd@ti.com>
Add initial SoC support for the TI J722s SoC series MAIN-domain
Cortex-R5 core.
TRM for J722s: https://www.ti.com/lit/zip/sprujb3
Signed-off-by: Andrew Davis <afd@ti.com>
This commit adds MBOX device tree entry for MCXN947.
Adds support for MCXN in NXP ipm and mbox drivers.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Move the Atmel SAM E70/V71 DMA PERIDs header file to
include/zephyr/dt-bindings/dma and unify it for use with the entire product
family (SAM E70/S70/V70/V71).
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Synchronize the Atmel SAM E70/V71 DMA Peripheral Hardware Requests HW
Interface Numbers and adjust them to match those listed in the SAM
E70/S70/V70/V71 datasheet.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Sort the Atmel SAMx7x periheral devicetree nodes according to their address
in the memory map.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
The Atmel SAM0 SoC enable peripherals clocks in distinct places: PM and
MCLK. The old devices had defined the peripheral clock enable bit at PM.
On the newer devices this was extracted on a dedicated memory section
called Master Clock (MCLK). This change excludes the dedicated bindings
in favor of a generic approach that cover all cases.
Now the clocks properties is complemented by the atmel,assigned-clocks
property. It gives the liberty to user to customize the clock source
from a generic clock or configure the direct connections.
All peripherals drivers were reworked with the newer solution.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Relocate the `power-states` node from under the `soc` node to
the `cpus` node, making it consistent with other STM32 SoC series.
This resolves the device-tree warning:
(simple_bus_reg): /soc/power-states: missing or empty reg/ranges property.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
TIM8 was missing from the dts board file. This is one of the
advandaced-control timers on the STM32H562xx/STM32H563xx processors.
Signed-off-by: Omeed Baboli <omeedbaboli@gmail.com>
- Add Flash HP support for ra6-cm4, ra6-cm33, ra4-cm33 (except
r7fa4w1ad2cng)
- Add config to set the minimal size of data which can be written
for RA4E2, RA4M2, RA4M3, RA6E1, RA6E2, RA6M1, RA6M2, RA6M3, RA6M4,
RA6M5
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
- Bring macro defined of RA8 in flash_hp_ra.h to device tree
- Change to use irq_lock instead of semaphore for code flash
- Modify and add conditions to check and make decision to perform
action at last block.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
