The exit latency and min residency is handled by sl_power_manager.
This improve power consumption by letting the device sleep longer.
Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
Add TI OMAP interprocessor mailbox nodes for AM62X A53,
the user ID assignment is as per thec corresponding mailbox
interrupt assignment for the core. Also while at it update the
supported feature list in corresponding boards.
More details can be found in the device TRM Mailbox section:
https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Add TI OMAP interprocessor mailbox nodes for AM62X M4,
the user ID assignment is as per thec corresponding mailbox
interrupt assignment for the core.
More details can be found in the device TRM Mailbox section:
https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
TI OMAP mailbox is the inter-processor mailbox IP found in TI
K3 devices (AM62X, AM64X, J721E .etc). The mailbox hardware uses
a queued mailbox interrupt mechanism that provides a communication
channel between processors through a set of registers and their
associated interrupt signals by sending and receiving messages.
The interrupt/bank associated with each processor entity is found
through the usr_id property from device tree.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Switch the default entropy driver for 54L05/10/15 devices to the new
CRACEN based one.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Change the property names in the bindings and overlay
to use hyphens(-) for separation instead of underscores(_).
Signed-off-by: James Roy <rruuaanng@outlook.com>
Add a new binding for STM32 RNG instances without interrupt lines,
such as the one present in the STM32WB05/06/07 SoCs.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The enet2 node in nxp_rt1060.dtsi incorrectly references &enet_ptp_clock
for its nxp,ptp-clock property. This commit updates the reference to
&enet2_ptp_clock.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Add `#address-cells = <0>;` to interrupt provider nodes in
the NXP S32 device tree to resolve warnings: e.g.
Warning (interrupt_provider): /soc/interrupt-controller@47800000: Missing
Warning (interrupt_provider): /soc/siul2@40520000/eirq0@40520010: Missing
This ensures compliance with device tree specifications and
eliminates build warnings.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This commit replaces a bunch of ifdefs and bindings with a single
extensible binding, and makes all standard mtime system timers consistent.
Signed-off-by: Camille BAUD <mail@massdriver.space>
In order to allow a custom disk name same as with the standard
sdmmc driver an additional device-tree property was introduced.
Signed-off-by: Carlo Kirchmeier <carlo.kirchmeier@zuehlke.com>
Split the USART driver into separate implementations for Silabs Series 2
and Series 0/1 boards. This change improves maintainability (especially
with the support of pin-ctrl and clock-ctrl on series 2 boards).
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
The on-board S26HS512T 512M-bit HyperFlash memory is connected to
the QSPI controller port A1.
This board configuration selects it as the default flash controller.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Add support HyperFlash memory devices on a NXP S32 QSPI bus.
This driver uses a fixed LUT configuration that defined in HAL RTD
HyperFlash driver.
Driver allows to read, write and erase HyperFlash devices.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Create common source code to use for supporting HyperFlash.
Rename 'FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME' to
'FLASH_NXP_S32_QSPI_SFDP_RUNTIME' as a common kconfig.
Add the 'max-program-buffer-size' property to use for
setting memory pageSize, instead of using
'CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE' for setting.
Add the 'write-block-size' propertyto use for setting
the number of bytes used in write operations, it also
uses to instead of the 'memory-alignment' property.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
The TMP435 is a remote temperature sensor monitor
with a built-in local temperature sensor.
Signed-off-by: Jaakko Rautiainen <jaakko.rautiainen@bittium.com>
For GIC multiple views feature support, all GIC Re-distributor's
GICR_TYPER.last will be set. Because configuration view-0 can
assign non-contiguous CPUs to views other than 0, in this case
the GIC Redistributors' registers won't seem contiguous.
So the GIC driver should cope with multiple sets of redistributors
like multi-chip scenarios. In this patch we add multiple GIC
redistributor regions support in GIC redistributor iteration.
For more information, refer to the Multi view subsection
in the GIC Technical Reference Manual.
For example:
https://developer.arm.com/documentation/101516/0400/Operation-of-GIC-700/Multi-view
Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
This commit adds asynchronous mode support to MAX32 UART driver. Each
direction uses a single DMA channel that is assigned in devicetree
configuration.
Asynchronous mode also depends on interrupts to refresh receive
timeouts.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
The MAX22017 is a two-channel industrial-grade software-configurable
analog output device that can be used in either voltage or current output
mode.
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Add comment to DTS file about SRAM partitions similar to the RTXXX
series has comments.
Add also a doc section to the frdm_rw612 about this.
Also fix the section hierarchy of the frdm_rw612 doc, the header levels
were wrong since the wifi and bluetooth, and reference sections were
under the debugging section.
Group all the wireless connectivity info together.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add support for the Antmicro's Myra SiP Baseboard. The board uses
Antmicro's Myra SiP which integrates STM32G491XX MCU and its SoC
configuration.
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Add `smb-wui` property to support wake-up from sleep mode by START
condition when i2c is configured to target mode.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add inverted flag to bindings, as pwms field is supposed
to be used by application only.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
This adds support PWM EMIOS for NXP S32Z SoC, both PWM pulse
generate and pulse capture are supported
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Removing period, duty and polarity configuration from
channel devicetree. At boot time, only minimal setup like
pinctrl, prescaler, etc should be initialized. PWM signal
is produced by using pwm_set* API
Also after this change, PWM period, duty are changed at the
next counter period boundary
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Fixes the CMake Warning on build/zephyr/zephyr.dts:
Warning (spi_bus_bridge): /soc/xspi@47001400: node name
for SPI buses should be 'spi'
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes the CMake Warning on build/zephyr/zephyr.dts:
Warning (spi_bus_bridge): /soc/octospi@52005000: node name
for SPI buses should be 'spi'
<stdout>: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge'
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes the CMake Warning on build/zephyr/zephyr.dts:
Warning (spi_bus_bridge): /soc/octospi@52005000: node name
for SPI buses should be 'spi'
<stdout>: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge'
Signed-off-by: Francois Ramu <francois.ramu@st.com>
