The OMAP I2C provides support for I2C serial interface on TI K3 series.
It is compatible with Philips I2C physical layer.
The commit includes:
Zephyr i2c api implementation
Polling Mode
Signed-off-by: Dhruv Menon <dhruvmenon1104@gmail.com>
TIM8 was missing from the dts board file. This is one of the
advandaced-control timers on the STM32H562xx/STM32H563xx processors.
Signed-off-by: Omeed Baboli <omeedbaboli@gmail.com>
Use a string for the xfr-min-bits property over an integer value, as this
significantly improves the readability of the MIPI DBI SPI device binding.
Signed-off-by: Stephan Linz <linz@li-pro.net>
- Add Flash HP support for ra6-cm4, ra6-cm33, ra4-cm33 (except
r7fa4w1ad2cng)
- Add config to set the minimal size of data which can be written
for RA4E2, RA4M2, RA4M3, RA6E1, RA6E2, RA6M1, RA6M2, RA6M3, RA6M4,
RA6M5
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
- Bring macro defined of RA8 in flash_hp_ra.h to device tree
- Change to use irq_lock instead of semaphore for code flash
- Modify and add conditions to check and make decision to perform
action at last block.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
This implements to generate the MAC address of the device UUID.
The UUID is hashed to reduce the size to 3 bytes.
Ideas taken from eth_nxp_enet.c
Adding dependencies on: HWInfo and CRC
Signed-off-by: Adib Taraben <theadib@gmail.com>
Fixes issue introduced in #76460
The previous code attempted to detect whether TMAG5273 or TMAG3001 was
connected based on DEVICE ID register. This doesn't work as the bits that
denote the version on one part are undefined on the other part, and cannot
be relied on to be zero.
This commit adds a TMAG3001 compatible which (for now) is just derived from
the TMAG5273 compatible. This allows TMAG3001 to be specified directly in
the DT. The driver code is updated to support both compatibles.
Signed-off-by: Yiding Jia <yiding.jia@gmail.com>
After updating the "st,stm32-vref" binding with a new property containing
the calibration data resolution ("vrefint-cal-resolution"), update the
corresponding nodes in SoC DTSI files with the proper value.
Note that the property is not set on SoCs with resolution of 12, as it is
the default value specified for the property in the binding.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add a property holding calibration resolution, similar to what already
exists in the st,stm32-temp-cal-common binding.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Refactor the devicetree files for the Atmel SAM E70 and SAM V71 product
series. These SoCs are part of a larger product family (SAM
E70/S70/V70/V71) and share a common set of peripherals.
Introduce a base samx7x.dtsi for all members of the family, containing the
union of all supported peripherals. Specific product series can use
/delete-node/ in their DTSI (e.g. same70.dtsi) for removing peripherals not
present in that product series.
Replace pin-count-specific DTSI files (e.g. same70q19b.dtsi) with
pin-count-agnostic DTSI files (e.g. same70x19b.dtsi) as the pin-count is
not taken into account in these anyways, and adjust the relevant board
devicetrees accordingly.
As part of this refactoring, introduce support for the missing flash memory
density variants of the SAM E70 product series.
Support for the two remaining product series (SAM S70/V70) is not part of
this refactoring as these will require further changes to the SoC support
code (soc/atmel/sam/).
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This is a squash of all the groundwork needed to
get a functioning driver for the DS3231 with the RTC API.
Signed-off-by: Gergo Vari <work@gergovari.com>
Some nodes in nRF54H20 DT files did not have a `reg` entry matching the
node address. While not used in practice, this aligns with the DT spec.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Fixes misassignment of cpuflpr_vevif label to cpuppr_vevif_tx node by
instead assigning to cpuflpr_vevif_tx node.
Signed-off-by: Daniel Mangum <georgedanielmangum@gmail.com>
Adds a dependency to `power.yaml`, as already exists for SPI and I2C
devices.
Signed-off-by: Stefan Schwendeler <Stefan.Schwendeler@husqvarnagroup.com>
The PL011 driver has already implemented supporting reset device
behavior.
However, the support is incomplete because the `arm,pl011.yaml`,
does not contain a `reset-device.yaml`.
Add include directive to `arm,pl011.yaml` to including
`reset-device.yaml` to complete the support for reset device.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add support for STM32H757 SoC, which shares its design
with STM32H747 with added cryptography peripherals.
Signed-off-by: Grzegorz Runc <g.runc@grinn-global.com>
Add the Sensor Fusion Low Power (SFLP) FIFO streaming capability,
using RTIO. The decode function is now aware of parsing following FIFO
tags:
- LSM6DSV16X_SFLP_GAME_ROTATION_VECTOR_TAG
- LSM6DSV16X_SFLP_GYROSCOPE_BIAS_TAG
- LSM6DSV16X_SFLP_GRAVITY_VECTOR_TAG
To activate SFLP the user should put in DT the proper configuration.
For example, to activate a 60Hz SFLP FIFO batching rate of game rotation
vector, gravity vector and gbias components, the user should add in DT
the following:
sflp-odr = <LSM6DSV16X_DT_SFLP_ODR_AT_60Hz>;
sflp-fifo-enable = <LSM6DSV16X_DT_SFLP_FIFO_GAME_ROTATION_GRAVITY_GBIAS>;
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The it8801 template is helpful but in the current state it does not
allow changing the device address as that is in the template itself. Fix
that by moving the template content down a level in the hierarchy, so
that it extends the mfd device itself rather than than instantiate it,
then the base instance can have any address, now the only limitation is
that only one instance is possible, but that is probably alright for
now.
Alternatives would be to use a define for the address, or even a
template per address, but this feels like a better compromise for now.
This may also use
https://github.com/zephyrproject-rtos/zephyr/pull/82825 in the future if
that ever becomes a thing.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The EFR32MG24B210F1536IM48 has 4 more GPIOs than the
EFR32MG24B310F1536IM48, and does not support the high accuracy
mode for the IADC.
Signed-off-by: Daniel Fuchs <software@sagacioussuricata.com>
Enables use of the counter dts property which allows to configure a counter
device as the timing source for the stepping.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
Adds a timing source api which is used by the step-dir stepper common code.
This allows the reusable common code to configure different timing sources,
since the initial delayable work implementation was inacurate for higher
maximum velocities.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
The LIS2DUXS12 is a smart, digital, 3-axis linear accelerometer whose
MEMS and ASIC have been expressly designed to combine the lowest current
consumption possible with features such as always-on antialiasing
filtering, a finite state machine (FSM) and machine learning core (MLC)
with adaptive self-configuration (ASC), and an analog hub / Qvar sensing
channel.
(https://www.st.com/en/mems-and-sensors/lis2duxs12.html)
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Avoid referring to Pico 2 (the name of a board). In this context,
RPI_PICO is used to refer to the (Zephyr) `SOC_FAMILY` rather than the
Pico 1 board. This clarifies common numerical values between the RP2040
and RP2350 SoC series, and enables existing DTS files to be used with
RP2350-based boards with fewer changes.
Remove the use of Zehpyr's `CONFIG_` macros from the device tree files,
and replace them with `SOC_SERIES`-specific files. Update the driver
implementation to conditionally include the correct file. Update
documentation and samples to match.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Add initial support for the RP2350's DMA peripheral, allow tests
under drivers/dma/loop_transfer to run on on the Raspberry Pi Pico 2,
and update the board's documentation.
Signed-off-by: Manuel Aebischer <manuel.aebischer@belden.com>
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Add initial support for the RP2350's PIO peripherals, extend the
existing example under samples/boards/raspberrypi/rpi_pico/uart_pio to
demonstrate this on the Raspberry Pi Pico 2, and update the board's
documentation.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Signed-off-by: Manuel Aebischer <manuel.aebischer@belden.com>
RP2350 is Raspberry Pi's newest SoC. From the datasheet:
"RP2350 is a new family of microcontrollers from Raspberry Pi that
offers significant enhancements over RP2040. Key features include:
• Dual Cortex-M33 or Hazard3 processors at 150 MHz
• 520 kB on-chip SRAM, in 10 independent banks
• 8 kB of one-time-programmable storage (OTP)
• Up to 16 MB of external QSPI flash/PSRAM via dedicated QSPI bus
...
"
This commit introduces some changes to support the existing RP2040 and
what is describe by Raspberry Pi as the "RP2350 family". Currently there
are 4 published products in the family: RP2350A, RP2350B, RP2354A, and
RP2354A. Within Zephyr's taxonomy, split the configuration as follows:
Family: Raspberry Pi Pico. This contains all RP2XXX SoCs,
SoC Series: RP2040 and RP2350.
SoC: RP2040 and, for now, just the RP2350A, which is present on the Pico
2, where the A suffix indicates QFN-60 package type. This structure is
reflected in `soc/raspberrypi/soc.yml`, and somewhat assumes that there
won't be a RP2050, for example, as a RP2040 with more RAM.
This is foundation work ahead of introducing support for Raspberry Pi's
Pico 2 board, which is fitted with a RP2350A and 4MB of flash.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add support for SoC-specific clock ids and update the initialization
function to support the existing RP2040 and add support for the RP2350.
clock_control_rpi_pico.c uses numerical values for clock ids taken from
rpi_pico_clock.h which are the "clock generator". For the RP2350 these
values are different for some of the same logical clock sources, as well
as the RP2040 and RP2350 having different clock sources available.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Add a GPIO driver for the Microchip MEC5 HAL based chips.
Current devices are: MEC174x, MEC175x, and HAL version of
MEC172x named MECH172x.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This adds initial support for NXP SDMA controller. We make use
of NXP HAL to configure the IP.
SDMA uses BD (buffer descriptors) to describe a transfer. We create
a cyclic list of descriptors and trigger them manually at start and
later when data is available.
This is tested using Sound Open Firmware app on top of Zephyr.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
- rename enable-gpios to en-gpios in adi,tmc2209
- place en-gpios in common stepper-controller.yaml
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Fast SPIM instances in nRF54H20 (SPIM120 and SPIM121) are driven by
the global HSFLL (HSFLL120). Add `clocks` property in these nodes
to reflect this.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
NXP FlexTimer Module is a configurable timer peripheral hence it should
be located under bindings/timer.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Rename "nxp,kinetis-ftm-pwm" compatible to "nxp,ftm-pwm" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Update the GC9X01X display driver binding documentation with the current
MIPI DBI SPI binding structure. The old example used direct SPI device
binding which is now deprecated in favor of the MIPI DBI API.
Signed-off-by: Benjamin Geiger <BenjaminGeiger1@gmail.com>
Add nrf twis (I2C controller supporting I2C peripheral role and
EasyDMA) support, including updating the existing twis dt binding
to match the hardware with proper examples.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
This patch adds support for HOST OpenThread communication to the RCP
co-processor via UART using SPINEL protocol.
The aim is to use OpenThread's RCP (Radio Co-Processor) with HOST device
(for example imxRT1020). Such configuration is the same as one used
with PC program (ot-cli) and RCP.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Removed FLASH_BASE_ADDRESS configuration from various boards' Kconfig.
The only thing needed in order to do this was to update the relevant dtsi
files so that the flash0 node has its reg property configured properly.
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
- provide support for the STM32C071 serie
- add stm32g0-flash-controller compatible on flash node
to fix CI issue on undefined reference to
`flash_stm32_page_layout'
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
The STM32F4 socs have different channels for the temperature sensor.
Some are at channel 16 and some at channel 18. Made changes wherever it
was relevant.
In short, the base configuration is to channel 16 and wherever it is
supposed to be 18 it is overridden.
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
Creation of the new zephyr\soc\nxp\common\nxp_nbu.c driver which manage
the interruption of the NBU. This modification is mandatory to support a
coex application which includes Bluetooth and 802.15.4 on the same
narrow band path.
Signed-off-by: Xavier Razavet <xavier.razavet@nxp.com>
This commit Introduces DTS configurations for DMA,
SPI, RNG, Crypto, USB and RTC modules to enable
support in STM32U0.
Signed-off-by: Mohammad Badawi <zephyr@exalt.ps>
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
Add dts node to support for gpio interrupt on Renesas RA SoC
- Add external interrupt node
- Add gpio interrupt pins
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
First commit to add support for gpio interrupt on Renesas RA
- Add support for external interrupt driver
- Add support for gpio interrupt config
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Move ioport6, ioport7, ioport8 to r7fa6m4ax due to it is common
part of RA6M4
Impacted file:
- dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi
- dts/arm/renesas/ra/ra6/r7fa6m4af3cfb.dtsi
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
In all STM32 dtsi and board dts, update the st,adc-sequencer and the
st,adc-clock-source properties so they are strings.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
fu dts: arm: st: use string instead of enum
STM32 sequencer property and clock source were defined using
arbitrary numbers. Use string instead.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
On STM32 ADC, there are currently two types of oversamplers (if present),
one with 8 available oversampling values, the other with 1024.
To simplify the driver, add the oversampler as a dts property.
Also add defines to avoid magic values in the dtsi.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
- Add "channel-available-mask" property in ADC node
to detect which channels are available to use
- Add "add-average-count" property in ADC node to chose
number of count of the addition or average mode
- Change the source code of ADC to match with 2 new properties.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
BICR (Board Information Configuration Registers) are located within the
application UICR region (ref. MRAM mapping, table 38).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add max22190 gpio driver with input functionality, since device
support only input without output.
Implemented diagnostic functionality for all 8 channels
which include various check to over/under voltage and wire break.
Filtering configuration is done from devicetree on per channel
bases and is configured on chip start.
In case some fault condition occure FAULT pin drive LOW which
prop to FAULT registers to be read. Data is stored in data structure
for furter analizes and ERR message is printed in console.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Add the power mode, accel and gyro filtering options,
and apex features. Add -p and -s compatible.
Signed-off-by: Aurelie Fontaine <aurelie.fontaine@tdk.com>
The samr21 is a samd21 with a builtin at86rf233 radio. Use the samd21 as
base for these SoC and drop all duplicated nodes.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The saml2x series provide USB to all SoC series. This moves the USB node
from saml21.dtsi to the base file saml2x.dtsi.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
When running tests on sam0 platform was detected that pinctrl for ADC
were not defined for some boards. To force an error at build time
nodes should be explicity disabled. This explicity disable nodes on
devicetree that require some user configuration.
In addition, the adc feature were excluded in some boards and
samr21-xpro was correct updated.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Keep a consistent order on the nodes definitions to make it easy to read
between all the SoC series.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add the ability to select littlefs disk version
to maintain backward compatibility
with existing littlefs
with the same major disk version.
Signed-off-by: Mikhail Siomin <victorovich.01@mail.ru>
LinkServer can flash only the first time, cannot flash again.
Fix it by setting default mcu security status as unsecure.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
The nrf-hsfll was previously the only supported HSFLL clock, hence it
was not namespaced fully. Since we added nrf-hsfll-global, we should
add the namespace to nrf-hsfll as well.
Updates drivers and devicetree uses of HSFLL as well.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add specific device model for global hsfll clock and update dts tree
to use specific model. The clock is not fixed, and configurable at
runtime to predefined frequencies specified by the platform.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Remove hard-coded clock values from device tree nodes,
instead read the clock values from the clock controller
during run time.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
The actual clock speed of the bus is partially determined by the
rising/falling edges of the SCL. These settings allow applications
to tune the clock based on board characteristics.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
Add a clk48Mhz node to the stm32f412 serie.
This clock is sourced by PLL_Q (default) or PLLI2S_Q
That 48MHz clock is used by the USB /SDMMC/RNG peripherals.
The sdmmc/SDIO clock is sourced by this CK48 (default)
or by the SYSCLOCK.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add power domains for EDMA0's channels 6, 7, 14, and 15.
For QM these are identified as IMX_SC_R_DMA_2_*, while
for QXP thy are identified as IMX_SC_R_DMA_0_*.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
