Add max22190 gpio driver with input functionality, since device
support only input without output.
Implemented diagnostic functionality for all 8 channels
which include various check to over/under voltage and wire break.
Filtering configuration is done from devicetree on per channel
bases and is configured on chip start.
In case some fault condition occure FAULT pin drive LOW which
prop to FAULT registers to be read. Data is stored in data structure
for furter analizes and ERR message is printed in console.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Add the power mode, accel and gyro filtering options,
and apex features. Add -p and -s compatible.
Signed-off-by: Aurelie Fontaine <aurelie.fontaine@tdk.com>
The samr21 is a samd21 with a builtin at86rf233 radio. Use the samd21 as
base for these SoC and drop all duplicated nodes.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The saml2x series provide USB to all SoC series. This moves the USB node
from saml21.dtsi to the base file saml2x.dtsi.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
When running tests on sam0 platform was detected that pinctrl for ADC
were not defined for some boards. To force an error at build time
nodes should be explicity disabled. This explicity disable nodes on
devicetree that require some user configuration.
In addition, the adc feature were excluded in some boards and
samr21-xpro was correct updated.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Keep a consistent order on the nodes definitions to make it easy to read
between all the SoC series.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add the ability to select littlefs disk version
to maintain backward compatibility
with existing littlefs
with the same major disk version.
Signed-off-by: Mikhail Siomin <victorovich.01@mail.ru>
LinkServer can flash only the first time, cannot flash again.
Fix it by setting default mcu security status as unsecure.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
The nrf-hsfll was previously the only supported HSFLL clock, hence it
was not namespaced fully. Since we added nrf-hsfll-global, we should
add the namespace to nrf-hsfll as well.
Updates drivers and devicetree uses of HSFLL as well.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add specific device model for global hsfll clock and update dts tree
to use specific model. The clock is not fixed, and configurable at
runtime to predefined frequencies specified by the platform.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Remove hard-coded clock values from device tree nodes,
instead read the clock values from the clock controller
during run time.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
The actual clock speed of the bus is partially determined by the
rising/falling edges of the SCL. These settings allow applications
to tune the clock based on board characteristics.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
Add a clk48Mhz node to the stm32f412 serie.
This clock is sourced by PLL_Q (default) or PLLI2S_Q
That 48MHz clock is used by the USB /SDMMC/RNG peripherals.
The sdmmc/SDIO clock is sourced by this CK48 (default)
or by the SYSCLOCK.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add power domains for EDMA0's channels 6, 7, 14, and 15.
For QM these are identified as IMX_SC_R_DMA_2_*, while
for QXP thy are identified as IMX_SC_R_DMA_0_*.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This has no address space and doesn't belong between peripheral
nodes. Move it up the DTSI for better visibility. No functional
change.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
imx8qm and imx8qxp have a couple of differences regarding
the peripheral address spaces and how the DT nodes are
configured, which is why using a generic DTSI (nxp_imx8.dtsi)
for the both of them is not right.
One of the differences between the two, which affects Zephyr
is the fact that irqstr's address space is different. Up until
now this has been dealt with at the board level (i.e:
imx8qxp_mek_mimx8qx6_adsp.dts), which is not right as this is not
board-specific, but rather soc-specific. Additionally, this
causes the following warning during compilation:
"unit address and first address in 'reg' (0x51080000) don't
match for /interrupt-controller@510a0000"
To fix this, add two new DTSIs: nxp_imx8qm and nxp_imx8qxp.
Each board (i.e: imx8qm_mek and imx8qxp_mek) will have to include
the DTSI for their soc instead of the generic DTSI (i.e: nxp_imx8).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
The Microchip CAP12xx series are available in 3, 6 or 8 channel versions.
Co-authored-by: Benjamin Cabé <kartben@gmail.com>
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
The reg address was not equal to the one in the node name, producing
a build warning.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Set AMP dts nodes (ipm, mbox, ...) to use fixed locations in reserved
memory areas. Those areas memories are delimited in the `memory.h`.
Size of the occupied areas can be calculated but the dts nodes addresses
needs to be set manually in every case.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This is the initial commit to support UART driver for Renesas RZ/G3S.
The driver only implements polling API for minimal support.
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/G3S
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This adds minimal support for a new SoC Renesas RZ/G3S
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
This commit adds the main DTS configurations required
to enable I3C support on STM32.
Signed-off-by: Mohammad Badawi <zephyr@exalt.ps>
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
LJ packages have 16 ADC channels vs 8 for SZ packages. Enhance
devicetree to account for this as well as conditional defines/code.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Due to Apollo3's internal bootloader, zephyr build is not able
to create correct flash address on linker.cmd while using
mcuboot. The PR configures flash-controller start address
to solve this problem.
Test board: rakwireless/rak11720
Test project: samples/subsys/mgmt/mcumgr/smp_svr
Signed-off-by: Sercan Erat <sercanerat@gmail.com>
This patch refactors the power management initialization for the SSP
driver across ACE15, ACE20, and ACE30 generations to align with the
recommended practices outlined in the documentation. The changes
include:
1. Replacing the conditional initialization of power management state
with a call to `pm_device_driver_init` in the `ssp_init` function.
2. Adding the `zephyr,pm-device-runtime-auto` property to the SSP nodes
in the device tree files for ACE15, ACE20, and ACE30.
3. Moving the power domain assignment for the SSP device in the device
tree. The previous configuration resulted in the device not being under
any power domain and being initialized as always ON.
These changes ensure that the SSP driver is initialized with the
appropriate power management state and that runtime power management is
automatically enabled based on the device tree configuration. The
functionality of the power management state remains unchanged, ensuring
consistent behavior.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch refactors the power management initialization for the DMIC
driver across ACE15, ACE20, and ACE30 generations to align with the
recommended practices outlined in the documentation. The changes
include:
1. Replacing the conditional initialization of power management state
with a call to `pm_device_driver_init` in the
`dai_dmic_initialize_device` function.
2. Adding the `zephyr,pm-device-runtime-auto` property to the DMIC nodes
in the device tree files for ACE15, ACE20, and ACE30.
These changes ensure that the DMIC driver is initialized with the
appropriate power management state and that runtime power management is
automatically enabled based on the device tree configuration. The
functionality of the power management state remains unchanged, ensuring
consistent behavior.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch addresses several issues with the Intel ADSP HDA DMA driver:
1. Refactors the HDA DMA power management initialization. The previous
use of `pm_device_runtime_enable` was incorrect. The updated approach
relies on enabling runtime power management through the device tree
using the `zephyr,pm-device-runtime-auto` property. Additionally, the
patch removes redundant device initialization steps as these are already
handled by `pm_device_driver_init` when the device is under a power
domain.
2. Corrects the power domain assignment for the HDA link. The HDA link
was previously assigned to the io0 power domain based on a
misinterpretation of the documentation. The correct power domain
assignment is now based on updated documentation for LNL, ensuring that
the HDA link is associated with the appropriate power domain.
These changes ensure that the HDA DMA driver properly manages power
states, reducing power consumption and improving system stability, while
ensuring the correct power domains are used.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch addresses the following issues with the Intel HDA DAI driver:
1. Adds power management support for the HDA DAI driver by implementing
the `hda_pm_action` function and integrating it with the Zephyr power
management framework.
2. Ensures balanced calls to `pm_device_runtime_get` and
`pm_device_runtime_put` by modifying the `probe` and `remove`
functions to use these power management calls.
3. Ensures that the io0 power domain is active when the HD Audio is in
use by assigning the correct power domain to the HDA DAI devices in
the device tree files for various Intel ADSP platforms (ace15_mtpm,
ace20_lnl, ace30, ace30_ptl).
4. Enables runtime power management for the HDA DAI devices by adding
the `zephyr,pm-device-runtime-auto` property in the device tree.
These changes ensure that the HDA DAI driver properly manages power
states, reducing power consumption and improving system stability, while
ensuring the io0 power domain is active when required.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Many MIPI DBI displays support a "tearing effect" signal, which can be
configured to signal each v-sync or h-sync interval. This signal can be
used by the MIPI DBI controller to synchronize writes with the
controller, and avoid tearing effects on the screen (which occur when
the write pointer from the MCU overlaps with the panel's read pointer in
the display controller's graphics RAM).
Add the `mipi_dbi_configure_te` API, which allows display controllers to
configure MIPI DBI controller to wait for a TE edge before streaming
display data. Allow the tearing enable parameters to be configured via
devicetree settings, since these will vary based on the MIPI DBI
controller and display controller in use.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Rename "nxp,kinetis-lpuart" compatible to "nxp,lpuart" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Introduce new binding "st,stm32u5-otghs-phy" for OTG_HS PHY. This allows to
configure clock source and handle STM32U5 specific OTG_HS PHY behavior in
driver implementation in a more readable way.
Move OTG_HS PHY clock selection (previously <&rcc STM32_SRC_HSI48
ICKLK_SEL(0)>) from OTG_HS node to OTG_HS PHY node.
Rename USBPHYC_SEL -> OTGHS_SEL which matches the definition in the stm32u5
CCIPR2 register (RM0456 Rev 5, Section 11.8.47).
Support enabling OTG_HS PHY clock, which is bit 15 (OTGHSPHYEN) in
RCC_AHB2ENR1. Change OTG_HS clock to be bit 14 (OTGEN).
Calculate in runtime OTG_HS PHY clock source frequency. Try to match that
to supported (16, 19.2, 20, 24, 26, 32 MHz) frequencies and select proper
option with HAL_SYSCFG_SetOTGPHYReferenceClockSelection() API (instead of
hardcoded 16 MHz selection).
Co-authored-by: Adrian Chadd <adrian.chadd@meta.com>
Signed-off-by: Adrian Chadd <adrian.chadd@meta.com>
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Support specifying divided clock buses by introduction of
STM32_CLOCK_DIV(div) macro. This macro can be used in devicetree to define
clock source of peripherals.
HSE is selected in devicetree using:
<&rcc STM32_SRC_HSE ...>;
HSE/2 can now be selected with:
<&rcc (STM32_SRC_HSE | STM32_CLOCK_DIV(2)) ...>;
This allows to use clock_control_get_rate() API in peripherals in order to
get desired clock rate.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Catch the DTS warning by copying the SDRAM node in description:
unit address and first address in 'reg' (0xc000000) don't match for
/sdram@c0000000
Signed-off-by: Haiyue Wang <haiyuewa@163.com>
for the brevity renaming direction_gpios to dir_gpios since STEP/DIR
interface is quite an established term in context of stepper controllers.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Additional bindings to configure SPI support.
Added new DTS option for data/IRQ sharing
Clarify default in driver DTS binding
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
This PR adds support for LAN9250 spi ethernet controller.
This driver is tested on the Mikroe ETH Click 3
https://www.mikroe.com/eth-3-click
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
The `ti,hdc20xx` is a common definition for TI HDC20xx series,
so the actual device named `hdc20xx` does not exist.
Remove the "compatible" section.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Extends the MIPI DBI SPI driver class for operating mode C4, SPI 4-wire,
with 16 write clocks to send one or multiple byte for commands. Generic
data (e.g. GRAM) aligned to 16-bit are passed through and stuffed with
bytes if required.
Signed-off-by: Stephan Linz <linz@li-pro.net>
New driver for Davicom DM8806 PHY. Driver is using standar mdio API
to manage the DM8806 switch controller. Register access needs the
PHY addres or switch address to be one of five possible values, since
DM8806 has built-in five PHY's. These values should be defined in the
application .dts file. One DM8806 ethernet port must corresponds with
one ethernet PHY node with two properties for ethernet port: one for
PHY address and one for switch address - <reg> for register access from
Internal PHY Register area and <reg-switch> for register access from
Switch Per-Port Registers area. Device tree example below:
example device-tree:
dm8806_phy: ethernet-phy@0 {
reg = <2>;
reg-switch = <8>;
compatible = "davicom,dm8806-phy";
status = "okay";
davicom,interface-type = "rmii";
reset-gpio = <&gpiod 2 GPIO_ACTIVE_LOW>;
interrupt-gpio = <&gpioc 1 GPIO_ACTIVE_HIGH>;
};
Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
Adds a step direction binding that can be used with any stepper that
implements said control interface to cut down on boilerplate code.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
Add tests for the new port / endpoint DT macros
Signed-off-by: Josuah Demangeon <me@josuah.net>
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Rename "nxp,kinetis-mpu" compatible to "nxp,sysmpu" to remove
the device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Rename "nxp,kinetis-dspi" compatible to "nxp,dspi" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The compatible: "st,stm32h7-hsi-clock" has HSI clock divider
required which is set to 1, by default, delevering 64MHz
in the stm32h7.dtsi and stm32h7rs.dtsi
(As done for stm32h5 and other series)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add a new implementation of a test pattern generator, with the same
architecture as real drivers: split receiver core and
I2C-controlled sub-device, with changes of video format in
"zephyr,emul-imager" leads to different data produced by
"zephyr,emul-rx".
Signed-off-by: Josuah Demangeon <me@josuah.net>
Depending on the stm32 serie the MCO1/2 prescaler is a value
set in the CFGR register to divide the MCO output clock.
Use the same model based on the RefMan for other stm32 series
than stm32C0/F4/F7/H5/H7, once the MCO is in the DTS.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Update discharge current limit property to be aligned
with the most recent npm1300 datasheet.
This affects the discharge current measurement calculation,
which needs to be scaled accordingly.
Signed-off-by: Audun Korneliussen <audun.korneliussen@nordicsemi.no>
Add `zephyr,memory-region-flags` for supporting memory region flags
setting.
For example, when the below node is in the devicetree,
```
test_sram: sram@20010000 {
compatible = "zephyr,memory-region", "mmio-sram";
reg = < 0x20010000 0x1000 >;
zephyr,memory-region = "FOOBAR";
zephyr,memory-region-flags = "rw";
};
```
We get the following line in MEMORY section of linker script.
```
FOOBAR (rw) : ORIGIN = (0x20010000), LENGTH = (0x1000)
```
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
- Fixes mcxw71 CI errors caused by wrong place
of the 'flash' node in DTS.
- Fixes mcxw71 build errors for storage, flash
and mcuboot examples.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
The Pico SDK defines a default value for its XOSC multiplier. Reflect
this in the device tree binding so that it doesn't need to be repeated.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Rename rpi_pico_common.dtsi to rp2040_reset.h . This is more consistent
with the wider Zephyr source tree, and is foundation work ahead of
introducing the RP2350 SoC.
Add missing include guard. This shouldn't be required, but it is
consistent with other header files in the same directory.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Follow the wider directory convention of dts/<arch>/<vendor>/<family>.
This is foundation work ahead of introducing support for the RP2350.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
This commit is to enable Ethernet drivers support on Renesas RA
MCU, first target support is the Renesas RA8 series
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Add support for mdio driver for Renesas RA MCU series
This support utilize the r_ether_phy driver in hal renesas
to support mdio write and read function
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Add support for GPIO controller feature of AW9523B.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Co-authored-by: Benjamin Cabé <kartben@gmail.com>
Add a definition of a STEMMA QT connector to which I2C
devices can be connected.
Since STEMMA-QT does not specify uses other than I2C,
this is just a formal definition.
(It may be helpful when using this connector as a GPIO,
which is not defined in STEMMA-QT)
Maybe in usual need to define i2c alias such like as,
```
stemma_qt_i2c: &i2c0 { }
```
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Co-authored-by: Benjamin Cabé <kartben@gmail.com>
Add watchdog driver for npm2100 pmic.
This pmic has one timer that can be used for multiple functions,
including a watchdog that can reset or power-cycle connected devices.
Signed-off-by: Audun Korneliussen <audun.korneliussen@nordicsemi.no>
Add sensor driver for npm2100 pmic.
This pmic performs measurements of battery voltage, regulator voltage
and die temperature.
Configurable pmic attributes are also organized under this driver.
Signed-off-by: Audun Korneliussen <audun.korneliussen@nordicsemi.no>
Add regulator driver for npm2100 pmic.
This pmic has one boost and one ldo regulator.
Signed-off-by: Audun Korneliussen <audun.korneliussen@nordicsemi.no>
Add mfd driver for the npm2100 pmic device.
The driver contains basic initialization routines,
and functionality not covered by other device driver APIs.
Signed-off-by: Audun Korneliussen <audun.korneliussen@nordicsemi.no>
Added dppic0 node label, alongside the dppic to maintain backward
compatibility. The use of dppic0 is preferred.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Add support for Norik Systems Octopus IO-Board based on
Norik Systems Octopus SoM.
Supported features:
- LTE-M/NB-IoT
- GPS
- LED
- 3-axis accelerometer
- Battery charger
- Solar charger
- SPI NOR flash
- Nano SIM connector
Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
Add support for setting the sample frequency via `attr_set` and the
output data rate from device tree source.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
IT8801 support GPIO alternate function switching.
Some GPIO pins can be switched as KSO or PWM function.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The IT8801 is an I/O expander that provides GPIO, PWM, Keyboard
functions via the I2C bus.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Rename "nxp,kinetis-adc12" compatible to "nxp,adc12" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Rename "nxp,kinetis-wdog32" compatible to "nxp,wdog32" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The DPPI and PPIB peripheral nodes must be enabled to allow the
CONFIG_HAS_HW_NRF_DPPIC to be set. This change is consistent with what
was done on nRF5340 and does not introduce any additional memory
overhead, because there is no Zephyr driver behind the nrf-dppic and
nrf-ppib bindings.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Allow configuring the clock prescaler divider for the NXP Kinetis
Timer/PWM Module (TPM). Setting the prescaler to a lower value
allows for higher resolution for the generated PWM waveforms.
This change is inspired from the pwm_mcux_ftm driver:
Link: https://github.com/zephyrproject-rtos/zephyr/pull/25396
Signed-off-by: Maximilian Werner <maximilian.werner96@gmail.com>
Apply nRF54H20 `min-residency-us` and `exit-latency-us` values for
existing power states.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Add 128 MHz clock source and use it for uart00. Baudrate setting
must be adjusted based on uart clock source so without this
change there is wrong baudrate on uart00.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add DT definitions for the RAK3172 LoRaWAN module, based on
STM32WLE5.
Ref. https://docs.rakwireless.com/product-categories/wisduo/
rak3172-module/low-level-development/
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
These devices have an architecturally fixed 13 MHz clock device. But
thankfully you can put a default into a DTS binding so we don't have
to repeat it for all of them.
Signed-off-by: Andy Ross <andyross@google.com>
In order for the driver to be compliant with the timing sequence
diagrams presented in the reference manual, the MCU has to wait
for some additional period of time while setting both the rs and rw
lines.
Signed-off-by: Jan Kuliga <jtkuliga@gmail.com>
Express delay values in nanoseconds. Set the default delay time values
as specified in the HD44780 reference manual.
Signed-off-by: Jan Kuliga <jtkuliga@gmail.com>
Separate the current driver for the FPGA iCE40 into two different ones.
One implements only the SPI load mode, the other one only the GPIO
bitbang mode.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
The GECKO_PIN() macro does not do anything except pass the
argument through unaltered. It only serves to make DeviceTree
files more verbose. It was inconsistently used, make the .dts
files consistent by never using it.
The DBUS pinctrl driver doesn't use the port or location macros
from the gpio_gecko.h header. The pin number macro is the only
other thing defined in this header. Stop including the header on
Series 2 based boards.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Swap from silabs,gecko-pinctrl to silabs,dbus-pinctrl for all boards
with Series 2 SoCs. Explicitly declare pin properties as part of
pinctrl pinout configuration.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Silicon Labs Series 2 and newer devices do alternate function
configuration fundamentally differently from Series 0 and 1. Pin routing
is done in a centralized fashion in the GPIO peripheral, as opposed to
having ROUTE registers in every peripheral. The concept of alternate
function location numbers also does not exist, functions are directly
assigned to GPIOs by their port and pin number.
This commit adds a new pinctrl driver for devices that use DBUS. It fully
makes use of pinctrl design principles as outlined in the Zephyr
documentation. The previous driver hard-codes pin properties such as filter
and pull-up/down in the driver itself, while the new driver leaves this up
to the user as configurable DeviceTree properties. The previous driver has
hard-coded support for UART, SPI and I2C, while the new driver has generic
support for all DBUS signals.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Flash node should not be under the peripheral bus, it is not a
peripheral. The base address of the flash was getting set correctly by
accident due to the fmu node mapping it out of the range of the
peripheral node by coincidence.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add RTIO async and RTIO stream functionalities that enables,
among all the other things, the sensor data streaming from FIFO.
RTIO stream is using both SENSOR_TRIG_FIFO_WATERMARK and
SENSOR_TRIG_FIFO_FULL triggers. The decoder currently only supports
following FIFO tags:
- LSM6DSV16X_XL_NC_TAG
- LSM6DSV16X_GY_NC_TAG
- LSM6DSV16X_TEMP_NC_TAG
Following FIFO parameters has to be defined in device tree to
correctly stream sensor data:
- fifo-watermark (defaults to 32)
- accel-fifo-batch-rate (defaults to LSM6DSV16X_DT_XL_NOT_BATCHED)
- gyro-fifo-batch-rate (defaults to LSM6DSV16X_DT_GY_NOT_BATCHED)
- temp-fifo-batch-rate (defaults to LSM6DSV16X_DT_TEMP_NOT_BATCHED)
Signed-off-by: Armando Visconti <armando.visconti@st.com>
In most implements, the msip base address is 0x2000000. But the address
is not fixed in all boards.
Signed-off-by: Yang Jialong <yangjialong@vcore.com>
Convert the eDMA compat to prop version for NXP S32Z2 SoC
that was missed in commit b070da7c33.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Since the label property from base.yaml is no longer deprecated, no need
to require to explicitly block it.
The only affected bindings seem to be these test bindings.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Label property is described in DT spec and does not need to be
deprecated in base.yaml anymore. It was originally deprecated to
discourage what was previously the most common use case of labels in
zephyr which was the old device_get_binding, which was rightfully
removed. However, labels do have a purpose as described in DT spec of
providing a human readable string to software to describe the device,
which there is some use for.
The description of a label should be given in the device binding, as
stated in DT spec.
Label properties should be of type string.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add devicetree node for code RAM, code RAM can be accessed
over AIXM bus or AXIF bus. Code access via AXIF interface
provides the best optimal performance
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Add `idle` and `s2ram` power states for nRF54H20 cpuapp and cpurad.
Also the substate `idle_cache_disable` added.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Introduce etrbuffer in the tddconf bindings to support flexible
placement in the memory map.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
This commit adds the pfic interrupt controller driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This commit adds the usart driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This commit adds the systick driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This commit adds the clock driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This commit adds the pinctrl driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This commit adds the dtsi and bindings for the WCH CH32V003 which is a
32-bit general-purpose RISC-V MCU.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
- Add SPI driver support for RA
- RA2A1 not support slave select keeping level so disable it
in Kconfig
Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Use a string for the mipi-mode property over an integer value, as this
significantly improves the readability of the MIPI DBI device binding.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The NXP LCDIC peripheral contains two internal timers, with configurable
periods. These times are used to determine delays within the peripheral,
such as the reset and tearing enable signal delays. Allow these periods
to be set within the devicetree for the peripheral.
Raise the period where required for display drivers that need a value
other than the reset setting
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Extend tca954x (tca9546a, tca9548a) driver to support tca9544a i2c MUX.
(different bitmask and flag for enable bit in register)
Signed-off-by: Florian Weber <Florian.Weber@live.de>
The NXP PORT pinmuxing peripheral is reused across the MCX, S32, and
Kinetis lines. Rename the compatible from the family-specific
nxp,kinetis-pinctrl to a more generic nxp,port-pinctrl to reflect the
actual name for the IP block used within reference manuals.
Update the NXP HAL revision to include a change to use the new Kconfig
name for the PORT pinctrl driver
Update the MAINTAINERS.yml path, as there are no longer any NXP drivers
matching the string "drivers/*/*kinetis*
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
* Replace copies of fixed-partitions nodes in related boards by
referencing the apropriate partition table from the available list.
* For better reference the `partitions_*.dtsi` file has boot offset,
purpose and the flash size encoded in the file name. Default flash size
is considered to be 4MB.
* Added the flash size node for the boards which are not based on the
module.
* Removed flash size registry from the esp32.*common.dtsi
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Split and fix the total SRAM size for STM32L4Px/L4Qx/L4Rx/L4Sx
device. Those MCUs with up to 640 Kbytes SRAM:
This is 640KB for the STM32L4Rxxx and STM32L4Sxxx devices :
• 192 Kbytes SRAM1 + 64 Kbytes SRAM2 + 384 Kbytes SRAM3
This is 320KB for the STM32L4P5xx and STM32L4Q5xx devices :
• 128 Kbytes SRAM1 + 64 Kbytes SRAM2 + 128 Kbytes SRAM3
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Split and fix the total SRAM size for STM32L47x/L48x/L49x/L4Ax
device. Those MCUs with up to 320 Kbytes SRAM:
• 96 Kbytes SRAM1 and 32 Kbyte SRAM2 on STM32L47x/L48x.
• 256 Kbyte SRAM1 and 64 Kbyte SRAM2 on STM32L49x/L4Ax
The sram0 node at address 0x20000000 and sram1 at address 0x10000000
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Replace the DT_INST_PROP_OR statements with defaults
in the devicetree binding of the iCE40.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
These two new ICs are variants of the nRF54L15 with different memory
sizes:
- nRF54L05: 500KB RRAM, 96KB RAM
- nRF54L10: 1022KB RRAM, 192KB RAM
- nRF54L15: 1524KB RRAM, 256KB RAM
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Removing direct #define usage in the DTSI file and converting these
definitions to use a dt-bindings header instead.
Relocates the RPI_PICO_DEFAULT_IRQ_PRIORITY definition to a DTSI file and
introduces an override.dtsi file. The override file is used when no other
override file is present, allowing for better flexibility and compliance
with Zephyr’s DTS structure.
Fixes: #79719
Signed-off-by: Tarang Raval <tarang.raval@siliconsignals.io>
Add `hifive_unmatched//s7` (earlier selected by default, using
`hifive_unmatched`) and `hifive_unmatched//u74` targets.
Define work-area for other 4 cores in openocd.cfg
Update twister platform white/black lists, to support new targets
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Add `hifive_unleashed//e51` (earlier selected by default, using
`hifive_unleashed`) and `hifive_unleashed//u54` targets.
Define work-area for other 4 cores in openocd.cfg
Update twister platform white/black lists, to support new targets
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Remove the renesas,ra-clock-generation-circuit driver, which is no longer
needed after migrating to the FSP-based implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Remove the renesas,ra-pinctrl driver, which is no longer
needed after migrating to the FSP-based implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add a common part for AMD board ACP_6_0_ADSP.
Add support for ACP_6_0_ADSP BOARD,
which represents ACP_6_0 soc.
This has a 1 Xtensa HiFi5 core, with 200-800MHz
1.75 MB HP SRAM / 512 KB IRAM/DRAM,
1 x SP (I2S, PCM), 1 x BT (I2S, PCM), 1 x HS(I2S, PCM), DMIC as
audio interfaces.
Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
A few bindings in the timer directory (for kernel timing sources) were
being used for counters (which can have alarms set, and have a distinct
API). Move these bindings to the counters directory.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added a binding description for the PPIB peripheral and added the device
tree nodes of the PPIB instances to the nRF54L15 and nRF54L20.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Convert the numerous revision compatibles to a DT property for the
revision called nxp,version (inspired from a linux DT property from
st called st,version on their DMA).
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This moves the SRAM definitions for STM32H56/7x chips up to the top
level since they are common to all of them.
Signed-off-by: Djordje Nedic <nedic.djordje2@gmail.com>
- stm32cO11/31 share the same spi peripheral
- include stm32_dma header to be able to configure
spi with dma config macros (STM32_DMA_PERIPH_TX,...)
in dts
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
The Xilinx AXI DMA Controller is commonly used in FPGA designs.
For example, it is a part of the 1G/2.5G AXI Ethernet subsystem.
This patch adds a driver for the Xilinx AXI DMA that supports
single MM2S and S2MM channels as well as the control and status
streams used by the AXI Ethernet subsystem.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
This commit changes the way some x86 devicetree set the unit-address values
of memory nodes. Before the change, they were always set to `0`. After the
change, they are derived from the `DT_DRAM_BASE` macro to match the first
address specified by the reg property.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
some flashes support special opcodes
for 4-byte addressing, that can be used
without switching to 4-byte mode.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Alder Lake have at least 2 cores. Both boards using this SoC
(up_squared_pro_7000 and adl) are configured with
MP_MAX_NUM_CPUS=2, so dts should contain at least one more core.
Signed-off-by: Franciszek Pindel <fpindel@antmicro.com>
Implement a new stable-poll-period-ms property to specify a new (slower)
polling rate for when the matrix is stable.
The keyboard thread can eat up a surprisingly high amount of cpu cycles in
busy waiting if the specific hardware implementation happen to have a
particularly slow settle time, but high frequency polling is really only
needed when debouncing.
The new property allow slowing down the polling rate when the matrix is
stable (either key pressed but none to be debounced or idle in the case
of the gpio implementation with no interrupts), this allows reducing the
overall cpu time taken by the keyboard scanning thread when keys are
persistently pressed.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The it8xxx2_kbd KSO pins can be used as both keyboard scan and GPIO. By
default the keyboard scanning driver controls the output level of all
the KSO signals from 0 to (col-size - 1), meaning that any line in
between used as GPIO is going to have its output value overridden.
Add a kso-ignore-mask property to the keyboard scan driver to allow
specifiying extra pins that should not be controlled by the driver.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This follows update of UTCPD.VBSCALE register field. It supports:
- "divide-20": External VBUS voltage divider circuit should be 1/20
for EPR application. The divided voltage compares with
200mV to set or clean VBUS Present bit.
- "divide-10": External VBUS voltage divider circuit should be 1/10
for SPR application. The divided voltage compares with
400mV to set or clean VBUS Present bit.
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
Add a driver for the MB85RSM1T FRAM chip.
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The HAL configuration binding can be done dynamically based on the
IP's address space. The `hal-cfg-index` property is more tied to
software rather than hardware so remove it as an attempt to clean
up the binding.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add USB node to apollo4p and apollo4p_blue qualifier, and apollo4p_evb
and apollo4p_blue_kxr_evb board to enableUSB support on the MCU and
its EVB.
Signed-off-by: Chew Zeh Yang <zeon.chew@ambiq.com>
Add npcm miscellaneous device control and power and clock control
instances.
Add device tree bindings for npcm power and clock control.
Signed-off-by: Alan Yang <tyang1@nuvoton.com>
Add initial support of the mailbox driver based
on the inter VM shared memory mechanism similar
as the existing IPM driver.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
With this change, the LPTIM counter will be able to set
its timeout to the st,timeout value. So that system can
sleep for that period without interruption.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Replace the enum for load modes for the iCE40 with a boolean flag,
as there are only two options:
- SPI: default, which should be used whenever possible
- GPIO bitbang: workarorund, in case a low-end microcontroller is used
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This will help distinguish 64 and 32-bit platforms by tooling, following
the pattern visible in e.g. RISC-V.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
Those dtsi are a base for a range of 32-bit platforms. Setting this
compatible makes it easier to distinguish all 32-bit x86 platforms.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
y
atom.dtsi enforces "intel,x86", but it doesn't help us discern if the
platform is 32 or 64-bit. We do that for example in RISC-V and it's
useful from the tooling perspective.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
This commit introduces the L2 Memory Capabilities (hsbcap) register node
to the Devicetree specifications for Intel ADSP ACE platforms. The
hsbcap register provides information on the general capabilities
associated with the L2 memory, which is critical for system
configuration and resource management. The hsbcap node has been added to
the Devicetree source files for ACE 1.5 (MTPM), ACE 2.0 (LNL), and ACE
3.0 (PTL) platforms.
In addition, the DFL2MM_REG macro in adsp_memory.h has been updated to
use the Devicetree node label for hsbcap, ensuring a consistent and
maintainable approach to accessing this register across the codebase.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
-Update formatting and contents of index.rst for cy8ckit_062s4
-Update formatting and contents of index.rst for cy8ckit_064s0s2_4343w
-Update formatting and contents of index.rst for cy8cproto_062_4343w
-Update formatting and contents of index.rst for cy8cproto_063_ble
-Update formatting and contents of index.rst for xmc45_relax_kit
-Update formatting and contents of index.rst for xmc47_relax_kit
-Change all instances of "PSoC" to "PSOC" for infineon platforms
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
Align the shared memories with the memory.h layout.
Reorder nodes to show memory related nodes together.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This bus type was originally created for what's today the ipc.c HCI driver.
Since this type hasn't yet been synced with BlueZ, rename it for
consistency, however leave the old define to not break backwards
compatibility with existing DT bindings (there are several more that use
"ipm" than ipc.c).
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
The authoritative source of these values is BlueZ:
https://git.kernel.org/pub/scm/bluetooth/bluez.git/tree/lib/hci.h#n38
Update our values with the above. The IPM definiton doesn't exist in
BlueZ, but should be added there to make sure we don't get out of sync
again.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Remove CONFIG_MMC_VOLUME_NAME, and set the disk name based on the
``disk-name`` property. This aligns with other disk drivers, and allows
for multiple instances of the mmc_subsys disk driver to be registered.
Add disk-name properties for all in tree definitions for the
mmc-subsys disk driver, and change all in tree usage of the disk name
Fixes#75004
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove CONFIG_SDMMC_VOLUME_NAME, and set the disk name based on the
``disk-name`` property. This aligns with other disk drivers, and allows
for multiple instances of the sdmmc_subsys disk driver to be registered.
Add disk-name properties for all in tree definitions for the
sdmmc-subsys disk driver, and change all in tree usage of the disk name
Fixes#75004
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The new update of clock device tree make the pll p q r clock
source cannot be choose by other node
This fix add 1 new dts binding for pll out p q r out line
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Define the "clocks" property, for the flash "st,stm32h7-flash-controller"
node, only for the stm32H7 dual-core devices
which have the RCC bit 8 present in their RCC AHB3 register.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the global power domain entry. This domain is not memory-mapped
but controlled using NRFS services.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit adjusts the sizes of the two PLIC nodes AE350 defines:
* `plic0` size is changed from `0x04000000` to `0x02000000`
* `plic_sw` size is changed from `0x04000000` to `0x00400000`
Without these change, `plic0` address space would overlap with `plic_sw`,
and with other memory-mapped peripherals.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The nrf7000, nrf7001 and nrf7002 expose a coex hardware interface
which is independent from the wifi/control interface (spi and
control pins)
These interfaces where previously combined into a single model. This
is incompatible with the actual usage of the interfaces where one
core may interact only with the coex interface, and another with the
wifi/control interface.
This commit moves the coex interface, commonly described in
"nordic,nrf70-coex.yaml", out of the wifi/control models
"nrf700<variant>-<bus>.yaml" to its own models
"nrf700<variant>-coex.yaml"
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
- Modify the macro in source code AGT to get the right data from
device tree
- Modify name of agt node
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
